Physically-aware$N$-detect ($PAN$-detect) test improves defect coverage by exploiting defect locality. This paper presents physically-aware test selection (PATS) to efficiently generate$PAN$-detect tests for large industrial designs. Compared to traditional$N$-detect test, the quality resulting from$PAN$-detect is enhanced without any increase in test execution cost. Experiment results from an IBM in-production application-specific integrated circuit demonstrate the effectiveness of PATS in improving defect coverage. Moreover, utilizing novel test-metric evaluation, we compare the effectiveness of traditional$N$-detect and$PAN$-detect, and demonstrate the impact of automatic test pattern generation parameters on the effectiveness of$PAN$-detect.

At-speed testing with functional speed clocks is often done using On-Product Clock Generation (OPCG). When test compression logic is also embedded within the circuit's DFT architecture, the loading of the OPCG programming bits can impact test compression results. We present an approach to the use of OPCG that enables high-speed testing and is compatible with test compression. It also enables the use of tests that pulse multiple domains to further reduce test time and data volume. It also supports generation of inter-domain and static ATPG tests. We present results on four designs; one design shows an over 35% reduction in patterns due to use of multiple clock domains per test. An additional 10+% savings is possible using side-scan to load the OPCG programming registers.

Product cost is a key driver in the consumer electronics market, which is characterized by low profit margins and the use of a variety of ldquobig-D/small-Ardquo mixed-signal system-on-chip (SoC) designs. Packaging cost has recently emerged as a major contributor to the product cost for such SoCs. Wafer-level testing can be used to screen defective dies, thereby reducing packaging cost. We propose a new correlation-based signature analysis technique that is especially suitable for mixed-signal test at the wafer-level using low-cost digital testers. The proposed method overcomes the limitations of measurement inaccuracies at the wafer-level. A generic cost model is used to evaluate the effectiveness of wafer-level testing of analog and digital cores in a mixed-signal SoC, and to study its impact on test escapes, yield loss, and packaging costs. Experimental results are presented for a typical mixed-signal ldquobig-D/small-Ardquo SoC, which contains a large section of flattened digital logic and several large mixed-signal cores.

Physically-aware N-detect attempts to improve the detection characteristics of traditional N-detect by exploiting the localized characteristics of defects. Specifically, in addition to detecting each fault N times, we also require that the physical neighborhood surrounding the target change state as well. In this work, the effectiveness of the physically-aware metric is examined using two approaches. First, tester responses from an in-production IBM chip are analyzed to compare the physically-aware N-detect test with other traditional tests that include stuck-at, IDDQ, logic BIST, and delay tests. Second, diagnostic results from LSI chip failures are utilized to directly compare the traditional and physically-aware N-detect metrics. Results from both experiments demonstrate the effectiveness of physically-aware N-detect test in detecting defects in modern industrial designs.

Product cost is a key driver in the consumer electronics market, which is characterized by low profit margins and the use of a variety of "big-D/small-A" mixed-signal system-on-chip (SoC) designs. Packaging cost has recently emerged as a major contributor to the product cost for such SoCs. Wafer-level testing can be used to screen defective dies, thereby reducing packaging cost. We propose a new correlation-based signature analysis technique that is especially suitable for mixed-signal test at the wafer-level using low-cost digital testers. The proposed method overcomes the limitations of measurement inaccuracies at the wafer-level. A generic cost model is developed to evaluate the effectiveness of wafer-level testing of analog and digital cores in a mixed-signal SoC, and to study its impact on test escapes, yield loss and packaging costs. Experimental results are presented for a typical mixed-signal "big-D/small-A" SoC, which contains a large section of flattened digital logic and several large mixed-signal cores.

Meeting the tight performance specifications mandated by the customer is critical for contract manufactured ASICs. To address this, at speed test has been employed to detect subtle delay failures in manufacturing. However, the increasing process spread in advanced nanometer ASICs poses considerable challenges to predicting hardware performance from timing models. Performance verification in the pres- ence of process variation is difficult because the critical path is no longer unique. Different paths become frequency limiting in different process corners. In this paper, we present a novel variation-aware method based on statistical timing to select critical paths for structural test. Node criticalities are computed to determine the probabilities of different circuit nodes being on the critical path across process variation.Moreover, path delays are projected into different process corners using their linear delay function forms. Experimental results for three multimillion gate ASICs demonstrate the effectiveness of our methods.

In contractmanufacturing, the circuit netlist is owned by the ASIC customer. The manufacturer is required to work strictly within the design structure established by the customer. To manufacture high-quality components in this environment, it is critical to meet the customer's mandated quality and performance criteria, while minimizing hardware overhead and introducing litle or no design change. In this paper, we present a test framework for contract-manufactured ASICs using low-cost testers. Key aspects of the framework are low hardware overhead, significant savings in test data volume and test cost, and tight integration of the at-speed and ATE-driven test components to the design and manufacturing process.

At-speed test of integrated circuits is becoming critical to detect subtle delay defects. Simulation-based functional test is difficult because low-cost testers are unable to supply multiple asynchronous clocks to the IC. Moreover, low-cost testers simply cannot operate at chip speed. Existing structural at-speed test methods are inadequate because they are unable to supply sufficiently-varied functional clock sequences to test complex sequential logic. Moreover, they require tight restrictions on the circuit design. In this paper, we present a new method for GHz-speed structural test of ASICs having no tight restrictions on the circuit design. In the present implementation, any complex at-speed functional clock waveform for 16 cycles can be applied. We also describe a method to test asynchronous clock domains simultaneously. Experimental results for two multi-million gate ASICs demonstrate high at-speed coverage.

Chip overheating has become a critical problem during test of today's complex core-based systems. In this paper, we address the overheating problem in network-on-chip (NoC) systems through thermal optimization using variable-rate on-chip clocking. We control the core temperatures during test scheduling by assigning different test clock frequencies to cores. We present two heuristics to achieve thermal optimization and reduced test time. Experimental results for example NoC systems show that the proposed method can guarantee thermal safety and yield better thermal balance, compared to previous methods using power constraints. Test application time is also reduced

Performance verification is becoming critical to high performance ASICs manufacturing. Performance verification ensures that only those ASICs whose performance is higher than an advertized threshold are shipped to demanding customers. This provides a means to weed out nominal performance ASICs, and also ship ASICs at difference grades. However, performance verification based on functional test requires high-functionality testers that can supply multiple asynchronous clocks. Additionally, functional test requires expensive testers that can operate at the speed of the fastest clock domain on the ASIC. As an alternative, at-speed structural test can provide performance verification capability at very low cost. However, existing structural test methods are inadequate because they are unable to supply sufficiently-varied functional clock sequences to test complex sequential logic. Moreover, they require tight restrictions on the circuit design. In this paper, we present a scalable and flexible structural test method for performance verification of GH-speed ASICs. The proposed method requires no tight restrictions on the circuit design. Moreover, low-cost testers are used, thus sharply reducing test cost.

At-speed test of integrated circuits is becoming critical to detect subtle delay defects. Existing structural at-speed test methods are inadequate because they are unable to supply sufficiently-varied functional clock sequences to test complex sequential logic. Moreover, they require tight restrictions on the circuit design. In this paper, we present a new method for at-speed structural test of ASICs, having no tight restrictions on the circuit design. In the present implementation, any complex at-speed functional clock waveform for 16 cycles can be applied. We present DFT structures that can generate high-speed launch-off-capture as well as launch-off-scan clocking without the need to switch a scan enable at-speed. We also describe a method to test asynchronous clock domains simultaneously. Experimental results on fault coverage and hardware measurements for three multi-million gate ASICs demonstrate the feasibility of the proposed approach

Chip overheating due to excessive and unbalanced power dissipation has become a critical problem during test of complex core-based systems. In this paper, we address the overheating problem in network-on-chip systems by using on-chip multiple-frequency clocking. We control the core temperatures during test scheduling by varying the test clock frequency assigned to each core, so that the power dissipation of each core during test can be adjusted individually and thermal balance is achieved. We present a heuristic where the optimization process can be integrated with test scheduling. Experimental results for NoC benchmarks show that the proposed method can guarantee thermal safety and yield better thermal balance.

Business demand for ultra-low defects-permillion (DPM) levels and the emergence of subtle defects that often manifest as functional errors only in the presence of certain specific environmental conditions such as crosstalk, have led to a critical need for intelligent, adaptive, and targeted defectoriented test. The classical model of test, in which integrated circuits (ICs) are subjected to a blanket suite of stuck-fault, transition and Iddq test patterns generated without consideration to layout and chip-to-chip differences are now insufficient to bring DPM levels for cutting-edge ICs down to the requisite 10-100 range demanded by qualityconscious customers.

This paper presents new results for intuitive teleoperation of continuous backbone "continuum" robot manipulators. Continuum robots present unique challenges due to the nonintuitive (to humans) nature of their basic movements. We present a series of mappings, at both position and velocity levels, which provide human operators with a versatile and intuitive suite of options for joystick control of continuum robots. Results from implementations on two types of continuum manipulator hardware are summarized.

Network-on-chip is the new paradigm in core-based system design. Reuse of the on-chip communication network for NoC test is critical to reduce test cost. However, efficient reuse of the communication network for test of legacy cores is challenging. A mismatch between the NoC channel width and the core test wrapper width can adversely affect test efficiency. In addition, stringent power constraints on today's high-density systems exacerbate the test scheduling problem. In this paper, we propose a method for efficiently utilizing the on-chip network for power-aware test scheduling in NoCs. We make use of on-chip clocking to speed up test data transfer by selectively using faster clocks to test certain cores; other cores receive slower clocks to limit test power consumption. A method is presented to determine the clock rate distribution among cores. Experimental results for the ITC '02 benchmarks show that the new method leads to substantial reduction in overall test application time, while satisfying power constraints.

Multilevel test access mechanism (TAM) optimization is necessary for modular testing of hierarchical systems-on-chip (SOCs) that contain older-generation SOCs as embedded megacores. We consider the case where these older-generation SOCs are used as hard cores in new SOC designs, and they are delivered to the system integrator as optimized and technology-mapped layouts. We present three hierarchical test planning and TAM optimization flows that exploit recent advances in TAM design for flattened SOC hierarchies. These techniques are based on the reuse of existing TAM architectures within megacores and the optimization of the top-level TAM under the constraints imposed by "TAM-ed" megacores that are delivered either with or without a wrapper. We present a new megacore wrapper-design technique for the latter case. Unlike prior methods that assume flat test hierarchies, the proposed methods are directly applicable to real-world design-transfer models involving hard megacores between the core vendor and the system integrator for hierarchical SOCs. Experimental results are presented for four ITC'02 SOC test benchmarks that contain megacores.

Recent advances in tester technology have led to automatic test equipment (ATE) that can operate at up to gigahertz speeds. However, system-on-chip (SOC) scan chains are typically run at lower frequencies, e.g., 10-50 MHz. The use of high-speed ATE channels to drive slower scan chains leads to an underutilization of resources, thereby resulting in an increase in SOC testing time. We present a new test planning technique to reduce the testing time and test cost by matching high-speed ATE channels to slower scan chains using the concept of virtual test access architectures. We also present a new test access mechanism (TAM) optimization framework based on Lagrange multipliers and analyze the impact of virtual TAMs on the overall SOC test power consumption for one of the ITC'02 benchmarks. Experimental results for TAM optimization based on Lagrange multipliers and virtual TAMs are presented for three industrial circuits from the set of ITC'02 SOC test benchmarks.

Recent advances in tester technology have led to automatic test equipment (ATE) that can operate at up to several hundred MHz. However, system-on-chip (SOC) scan chains typically run at lower frequencies (10-50 MHz). The use of high-speed ATE channels to drive slower scan chains leads to an underutilization of resources, thereby resulting in an increase in testing time. We present a new technique to reduce the testing time and test cost by matching high speed ATE channels to slower scan chains using the concept of virtual test access mechanisms (TAMs). We also present a new TAM optimization framework based on Lagrange multipliers. Experimental results are presented for three industrial circuits from the ITC'02 SOC test benchmarks.

Multi-level TAM optimization is necessary for modular testing of hierarchical SOCs that contain older-generation SOCs as embedded cores. We present two hierarchical TAM optimization flows that exploit recent advances in TAM design for flattened SOC hierarchies. Unlike prior methods that assume flat test hierarchies, the proposed methods are directly applicable to real-world design transfer models between the core vendor and the SOC integrator. Experimental results are presented for four ITC'02 SOC test benchmarks.

We describe an integrated framework for system-on-chip (SOC) test automation. Our framework is based on a new test access mechanism (TAM) architecture consisting of flexible-width test buses that can fork and merge between cores. Test wrapper and TAM cooptimization for this architecture is performed by representing core tests using rectangles and by employing a novel rectangle packing algorithm for test scheduling. Test scheduling is tightly integrated with TAM optimization and it incorporates precedence and power constraints in the test schedule, while allowing the SOC integrator to designate a group of tests as preemptable. Test preemption helps avoid hardware and power consumption conflicts, thereby leading to a more efficient test schedule. Finally, we study the relationship between TAM width and tester data volume to identify an effective TAM width for the SOC. We present experimental results on our test automation framework for four benchmark SOCs.

Test access mechanisms (TAMs) are an important component of a system-on-chip (SOC) test architecture. TAM optimization is necessary to minimize the SOC testing time. We present a fast, heuristic technique for TAM optimization and demonstrate its scalability for several industrial SOCs. Since the TAM optimization problem is NP-hard, recently proposed methods based on integer linear programming and exhaustive enumeration can be used to design limited test architectures with only a very small number of TAMs in a reasonable amount of time. In this paper, we explore a larger solution-space to design efficient test architectures with more TAMs. We show that the SOC testing times obtained using the new heuristic algorithm are comparable to or lower than the testing times obtained using enumeration. Moreover, significant reduction can be obtained in the CPU time compared to enumeration.

Test planning for core-based system-on-a-chip (SOC) designs is necessary to reduce testing time and test cost. In this paper we survey recent advances in test planning that address the problems of test access and constrained test scheduling for core-based SOCs. We describe several test access architectures proposed by research groups in industry and academia, as well as a wide range of methodologies for the optimization of such architectures. An extensive list of references to prior and current work in the SOC test planning domain is included.

This paper describes an integrated framework for plug-and-play SOC test automation. This framework is based on a new approach for wrapper/TAM co optimization based on rectangle packing. We first tailor TAM widths to each core's test data needs. We then use rectangle packing to develop an integrated scheduling algorithm that incorporates precedence and power constraints in the test schedule, while allowing the SOC integrator to designate a group of tests as preemptable. Finally, we study the relationship between TAM width and tester data volume to identify an effective TAM width for the SOC. We present experimental results for non-preemptive, preemptive, and power-constrained test scheduling, as well as for effective TAM width identification for an academic benchmark SOC and three industrial SOCs.

Core test wrappers and test access mechanisms (TAMs) are important components of a system-on-chip (SOC) test architecture. Wrapper/TAM co-optimization is necessary to minimize the SOC testing time. Most prior research in wrapper/TAM design has addressed wrapper design and TAM optimization as separate problems, thereby leading to results that are sub-optimal. We present a fast heuristic technique for wrapper/TAM co-optimization, and demonstrate its scalability for several industrial SOCs. This extends recent work on exact methods for wrapper/TAM co-optimization based on integer linear programming and exhaustive enumeration. We show that the SOC testing times obtained using the new heuristic algorithm are comparable to the testing times obtained using exact methods. Moreover more than two orders of magnitude reduction can be obtained in the CPU time compared to exact methods. Furthermore, we are now able to design efficient test access architectures with a larger number of TAMs.

We present a two-step solution to the problem of test resource optimization for multi-site testing of embedded-core-based SOCs. In step 1, an efficient technique based on enhanced rectangle packing is used to design the wrapper/TAM (test access mechanisms) architecture such that the SOC test suite fits in a single ATE memory load. Furthermore, the total TAM width for the SOC is minimized, thereby reducing routing complexity and hardware cost. Minimum TAM width directly leads to the minimization of the number of ATE channels used, thus enabling multi-site testing. In step 2, test scheduling is performed such that "idle" bits appearing between core tests on ATE channels are moved to the end of each channel. This reduces the memory depth allocated to the channels from the pool of ATE memory. The saved memory can be mapped to the remaining ATE channels to test other SOCs, thereby further facilitating multi-site testing. We present experimental results on our technique for five benchmark SOCs.

Test scheduling and TAM (test access mechanism) optimization for core-based SoCs is a challenging problem. Test schedules must be crafted with the objectives of minimizing testing time to reduce test cost, under the constraints of total available TAM width. Moreover precedence relations and power constraints must be met to ensure safe, effective, and high-quality testing. Prior research in test scheduling has mainly used constructive approaches such as rectangle packing to solve this problem, but these approaches fail to address the problem of creating a simple, standard representation for SoC test schedules that can be used by a wide range of optimization algorithms. In this paper we present a novel and efficient method to represent SoC test schedules and TAM width assignment based on the use of k-tuples. The proposed approach provides a compact, standardized representation of test schedules. This facilitates fast and efficient evaluation of SoC test automation solutions to reduce test costs. We propose heuristic algorithms based on the use of k-tuples to solve scheduling problems for SoCs in an efficient manner; extensions to our method to incorporate precedence relations among tests and power constraints in the schedule are also presented. Finally, experimental results using the new ITC'02 SoC benchmarks validate the quality of our solutions.

This paper presents the ITC'02 SOC test benchmarks. The purpose of this new benchmark set is to stimulate research into new methods and tools for modular testing of SOCs and to enable the objective comparison of such methods and tools with respect to effectiveness and efficiency. The paper defines the benchmark format and naming scheme, and presents the benchmark SOCs. In addition, it provides an overview of the research problems that can be addressed and evaluated by means of this benchmark set. These research problems include the design of optimized test access infrastructures and test schedules.

The testing time for a system-on-chip (SOC) is determined to a large extent by the design of test wrappers and the test access mechanism (TAM). Wrapper/TAM co-optimization is therefore necessary for minimizing SOC testing time. We recently proposed an exact technique for co-optimization based on a combination of integer linear programming (ILP) and exhaustive enumeration. However, this approach is computationally expensive for large SOCs, and it is limited to fixed-width test buses. We present a new approach for wrapper/TAM co-optimization based on generalized rectangle packing, also referred to as two-dimensional packing. This approach allows us to decrease testing time by reducing the mismatch between a core's test data needs and the width of the TAM to which it is assigned. We apply our co-optimization technique to an academic benchmark SOC and three industrial SOCs. Compared to the ILP-based technique, we obtain lower or comparable testing times for two out of the three industrial SOCs. Moreover, we obtain more than two orders of magnitude decrease in the CPU time needed for wrapper/TAM co-design.

System-on-a-chip (SOC) designs present a number of unique testability challenges to system integrators. Test access to embedded cores often requires dedicated test access mechanisms (TAMs). We present an improved approach for designing efficient TAMs and investigate the problems of improved deserialization of test data in the core wrapper, optimal test bus sizing, and optimal assignment of cores to test buses in the system. Place-and-route and power constraints are incorporated in the model. This work represents an important first step towards combining TAM design with efficient wrapper design for test data deserialization. Experimental results demonstrate that the proposed TAM optimization methodology provides efficient test bus designs for minimizing the testing time.

Test scheduling is an important problem in system-on-a-chip (SOC) test automation. Efficient test schedules minimize the overall system test application time, avoid test resource conflicts, and limit power dissipation during test mode. In this paper, we present an integrated approach to several test scheduling problems. We first present a method to determine optimal schedules for reasonably sized SOCs with precedence relationships, i.e., schedules that preserve desirable orderings among tests. We also present an efficient heuristic algorithm to schedule tests for large SOCs with precedence constraints in polynomial time. We describe a novel algorithm that uses preemption of tests to obtain efficient schedules for SOCs. Experimental results for an academic SOC and an industrial SOC show that efficient test schedules can be obtained in reasonable CPU time.

Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip (SoC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrapper design problem at a time, i.e., either optimizing the TAMs for a set of pre-designed wrappers, or optimizing the wrapper for a given TAM width. In this paper, we address a more general problem, that of carrying out TAM design and wrapper optimization in conjunction. We present an efficient algorithm to construct wrappers that reduce the testing time for cores. Our wrapper design algorithm improves on earlier approaches by also reducing the TAM width required to achieve these lower testing times. We present new mathematical models for TAM optimization that use the core testing time values calculated by our wrapper design algorithm. We further present a new enumerative method for TAM optimization that reduces execution time significantly when the number of TAMs being designed is small. Experimental results are presented for an academic SoC as well as an industrial SoC.

Test scheduling is a major problem in system-on-a-chip (SOC) test automation. We present an integrated framework that addresses several important test scheduling problems. We first present efficient techniques to determine optimal SOC test schedules with precedence constraints, i.e., schedules that preserve desirable orderings among tests. We then present a new algorithm that uses preemption to obtain optimal test schedules in polynomial time. Finally, we present a new method for determining optimal power-constrained schedules. Experimental results for a representative SOC show that test schedules can be obtained in reasonable CPU time for all cases.

We present a new approach for built-in test pattern generation based on the reseeding of twisted-ring counters (TRCs). The proposed technique embeds a precomputed deterministic test set for the circuit under test (CUT) in a short test sequence produced by a TRC. The TRC is designed using existing circuit flip-flops and does not add to hardware overhead beyond what is required for basic scan design. The test control logic is simple, uniform for all circuits, and can be shared among multiple CUTs. Furthermore, the proposed method requires no mapping logic between the test generator circuit and the CUT; hence it imposes no additional performance penalty. Experimental results for the ISCAS benchmark circuits show that it is indeed possible to embed the entire precomputed test set in a TRC sequence using only a small number of seeds.

We present a new approach for built-in pattern generation based on the reseeding of twisted-ring counters (TRCs). The proposed technique embeds a precomputed deterministic test set for the circuit under test (CUT) in a short test sequence produced by a TRC. The TRC is designed using existing circuit flip-flops and does not add to hardware overhead beyond what is required for basic scan design. The test control logic is simple, uniform for all circuits, and can be shared among multiple CUTs. Furthermore, the proposed method requires no mapping logic between the TGC and the CUT; it imposes no additional performance penalty. Experimental results for the ISCAS benchmark circuits show that it is indeed possible to embed the entire precomputed test set in a TRC sequence using only a small number of seeds, especially if the test set contains many don't-cares.

We present a new approach to built-in self-test of sequential circuits using precomputed test sets. Our approach is especially suited to circuits containing a large number of flip-flops but few primary inputs. Such circuits are often encountered as embedded cores and filters for digital signal processing, and are inherently difficult to test. We show that statistical encoding of test sets can be combined with low-cost pattern decoding for deterministic BIST. This approach exploits recent advances in sequential circuit ATPG and unlike other BIST schemes, does not require access to gate-level models of the circuit under test. Experimental results show that the proposed method provides higher fault coverage than pseudorandom testing with shorter test application time.

We present an efficient hardware implementation of a Huffman decoding algorithm that is based on the prefix-free property of Huffman codes. The proposed method can be used to reduce tester memory requirements for integrated circuit testing.