Recently, various intrusion detection systems (IDSs) have been proposed for in-vehicle networks. However, as vehicle network attacks become increasingly sophisticated, existing IDSs have shown limitations in effectively detecting new threats. In particular, supervised learning-based IDSs are incapable of detecting previously unseen attacks. On the other hand, while unsupervised learning-based IDSs can detect such attacks, they often suffer from relatively low detection performance. To address these limitations, we propose a semi-supervised generative adversarial network (SGAN)-based IDS for in-vehicle networks. In our proposed SGAN, the adversarially trained discriminator serves as an anomaly detector. Furthermore, we enhance the discriminator’s detection capability by incorporating labeled attack data during training. For instance, a discriminator trained on three distinct types of attacks can effectively detect unknown attack type. This approach enables more accurate and robust distinction between normal and attack data. Experimental results demonstrate that our proposed approach is suitable for in-vehicle network security, achieving an average detection accuracy of 99.63% and a precision of 99.52% for unknown attack types.

This paper introduces a novel intrusion detection system (IDS) suitable for both CAN and CAN-FD protocols, which are widely used in vehicle networks. Since most existing machine learning-based IDS are designed without considering the CAN-FD data frame, their application to CAN-FD systems increases model complexity or complicate implementation. This issue is particularly noticeable in models that use data payloads as input features, since CAN allows data payloads of up to 8 bytes, whereas CAN-FD is capable of up to 64 bytes. To address this problem, we propose a novel approach that utilizes CAN ID and CRC fields. This is because the CRC field is calculated based on the data field in both CAN and CAN-FD protocols, which eliminates the need to separately adopt the data field as a feature. We evaluated the performance of an LSTM-based IDS trained with these features. Experimental results confirm that our IDS achieves near-perfect detection performance and is significantly more lightweight compared to existing models.

This paper designs and implements a novel Temporal difference based adaptive object Detection (ToDo) platform in the video analytics at edge computing system. The proposed ToDo platform contains object tracking function and monitoring function, respectively. Based on temporal difference, the proposed ToDo skips the frames for object detection through adaptively controlling object detection rates. Then, it provides a monitoring function of object tracking and resource usages. The proposed ToDo platform is implemented on commercial edge node Jetson TX2 by utilizing YOLO (You Only Look Once) v3, and Dashboard, respectively. We evaluate its performance through extensive measurement-based analysis, and reveal that the proposed ToDo reduces GPU memory footprint to 17% while conducting moving objects detection with 7% accuracy loss.

This paper presents a fast and robust plane feature extraction and matching technique for RGB-D type sensors. We propose three algorithm components required to utilize the plane features in an online Simultaneous Localization and Mapping (SLAM) problem: fast plane extraction, frame-to-frame constraint estimation, and plane merging. For the fast plane extraction, we estimate local surface normals and curvatures by a simple spherical model and then segment points using a modified flood fill algorithm. In plane parameter estimation, we suggest a new uncertainty estimation method which is robust against the measurement bias, and also introduce a fast boundary modeling method. We associate the plane features based on both the parameters and the spatial coverage, and estimate the stable constraints by the cost function with a regulation term. Also, our plane merging technique provides a way of generating local maps that are useful for estimating loop closure constraints. We have performed real-world experiments at our lab environment. The results demonstrate the efficiency and robustness of the proposed algorithm.

In this paper, a readout circuit with a novel two-stage amplification method is presented for current sensing of 64-channel CNT(carbon nanotube) arrays. Key blocks of the proposed readout circuit consist of a transimpedance amplifier (TIA) block and an 11-bit SAR-ADC. In whole sensing sequence, the TIA block converts sensing currents of 64-channel CNT sensors into corresponding voltage levels through 64 active input current mirrors (AICMs) and a shared variable gain amplifier (VGA). This amplification method uses only one VGA requiring a high power consumption and large area for passive elements. Therefore, the proposed two-stage amplification method can be designed with small area and low power. Also, the output of the VGA is digitalized using the SAR-ADC with adaptive resolutions based on lower bit skipping algorithm according to an input voltage level for low power operation. The readout circuit is designed with the area of 0.173 mm2in 0.13 μm CMOS technology. The power consumption is measured about 73.06 μW at the conversion rate of 640 S/s.

In this paper, we develop a new framework for simultaneous localization and mapping (SLAM) based on Rao-Blackwellized particle filters (RBPF), that can be applied to floor-cleaning robots which are equipped with sparse and short-range sensors. To overcome the sensor limitations, the entire region is divided into several local maps, which are assumed to be independent to each other. The local maps are estimated by a local RBPF SLAM, and then the trajectory of the local map origin is estimated by a global RBPF SLAM. To compensate for the severe sensing limitations, we also adopt the assumption that the indoor environments consist of many orthogonal lines. This assumption significantly enhances the filter performance. The proposed SLAM framework is combined with a coverage path planning algorithm, and the resulting robot system is capable of online simultaneous coverage and SLAM. The algorithm was embedded into a real mobile robot platform and tested in a real home environment to assess the robustness of the proposed method.

This paper presents a novel area-efficient truncated inversionless Berlekamp-Massey (TiBM) architecture for Reed- Solomon decoders. Especially this paper proposes how to truncate processing elements (PE) in order to reduce the hardware complexity of key equation solver (KES) block. The RS decoder using proposed TiBM architecture has been designed and implemented by 90-nm CMOS standard cell technology with a supply voltage of 1.1 V. The RS decoder using proposed TiBM architecture operates at a clock frequency of 400 MHz and has a throughput of 3.2 Gb/s. The proposed architecture requires approximately 25.4% fewer gate counts than architecture based on the conventional RiBM algorithm.

A sequence of images in multiple views rather than a single image from a single view is of great advantage for robust visual recognition and pose estimation of 3D objects in noisy and visually not-so-friendly environments (due to texture, occlusion, illumination, and camera pose). In this paper, we present a particle filter based probabilistic method for recognizing an object and estimating its pose based on a sequence of images, where the probability distribution of object pose in 3D space is represented by particles. The particles are updated by consecutive observations in a sequence of images and are converged to a single pose. The proposed method allows an easy integration of multiple evidences such photometric and geometric features as SIFT, color, 3D line, 2D square, etc. The integration of multiple evidences, including photometric and geometric features, in space and time makes the proposed method robust to various not-so-friendly visual environments. The experimental results with a single stereo camera show the validity of the proposed method in an environment containing both textured and texture-less objects.

We propose an intra-task voltage scheduling algorithm for low-energy hard real-time applications. Based on a static timing analysis technique, the proposed algorithm controls the supply voltage within an individual task boundary. By fully exploiting all the slack times, a scheduled program by the proposed algorithm always complete its execution near the deadline, thus achieving a high energy reduction ratio. In order to validate the effectiveness of the proposed algorithm, we built a software tool that automatically converts a DVS-unaware program into an equivalent low-energy program. Experimental results show that the low-energy version of an MPEG-4 encoder/decoder (converted by the software tool) consumes less than 7$\sim$25% of the original program running on a fixed-voltage system with a power-down mode.

A novel hardware-software cooperative power control scheme, namely a software feedback loop, is proposed to lower power consumption of VLSI systems.The proposed runtime voltage and frequency control scheme guarantees the realtime execution of applications.It avoids interface problems and also provides "binary-code compatibility".Using a software analysis environment, the power control scheme is shown to achieve more than 90% power reduction for real-time MPEG-4 SP@L1 video encoding, taking into consideration the transition delay between voltage and frequency levels.

This paper presents a novel run-time dynamic voltage scaling scheme for low-power real-time systems. It employs software feedback control of supply voltage, which is applicable to off-the-shelf processors. It avoids interface problems from variable clock frequency. It provides efficient power reduction by fully exploiting slack time arising from workload variation. Using software analysis environment, the proposed scheme is shown to achieve 80~94% power reduction for typical real-time multimedia applications.

This paper describes a new motion estimation algorithm that is suitable for hardware implementation and substantially reduces the hardware cost by using a low bit-resolution image in the block matching. In the low bit-resolution image generation, adaptive quantization is employed to reduce the bit resolution of the pixel values, which is better than simple truncation of the least significant bits in preserving the dynamic range of the pixel values. The proposed algorithm consists of two search steps: in the low-resolution search, a set of candidate motion vectors is determined, and in the full-resolution search, the motion vector is found from these candidate motion vectors. The hardware cost of the proposed algorithm is 1/17 times of the full search algorithm, while its peak signal-to-noise ratio is better than that of the 4:1 alternate subsampling for the search range of /spl plusmn/32/spl times//spl plusmn/32. A VLSI architecture of the proposed algorithm is also described, which can concurrently perform two prediction modes of the MPEG2 video standard with the search range of (-32.0,-32.0)-(+31.5,+31.5). We fabricated a MPEG2 motion estimator with a 0.5-/spl mu/m triple-metal CMOS technology. The VLSI chip includes 110 K gates of random logic and 90 K bits of SRAM in a die size of 11.5 mm/spl times/12.5 mm. The full functionality of the fabricated chip was confirmed with an MPEG2 encoder chip.

We propose a new motion estimation algorithm using low-resolution quantization. The proposed algorithm reduces both performance degradation and computational cost by matching at every search position with a low bit resolution image. It consists of two steps: the low resolution search that generates the candidate motion vectors and the full-resolution search that finds the best motion vector in the candidates from the low-resolution search. Simulation results show that the PSNR of the proposed algorithm is superior to that of the 4:1 alternate subsampling algorithm and the one-dimensional full search algorithm with less computational cost. The PSNR degradation of the proposed algorithm with respect to the full search algorithm is less than 0.12 dB with 1/17.7 computational cost.