As semiconductor technology advances, radiative-particle-induced soft errors and power consumption are becoming major concerns for digital circuits in aerospace applications. Radiation hardening by design and magnetic tunnel junctions (MTJs) are widely employed to address these concerns. In this paper, a novel latch, called TNURML, that can completely recover from triple-node upsets (TNUs), is proposed. The embedded MTJs provide non-volatility and are compatible with traditional CMOS processes. The TNURML employs a TNU-recovery module as well as a pair of MTJs for backup and recovery operations. Extensive simulations demonstrate the excellent TNU-recovery capability and non-volatility of the TNURML latch at the cost of slightly increased area overhead. The proposed TNURML latch reduces 43.63% of delay and 48.23% of power on average when compared to the state-of-the-art latches.

The true random number generator (TRNG) is capable of generating completely random and unpredictable sequences. TRNG is an important hardware security primitive, it plays a critical role in identity verification, prevention of replay attacks and key exchange. To meet the demand for high-throughput true random number generators in modern high-speed systems, a lightweight design is proposed. It utilizes a mesh topological of coupled-XOR as entropy source and generates a highly compact and high throughput true random number generator by coupling oscillators in the network. The generated random sequences have successfully passed the NIST SP800-22 and AIS-31 tests. It achieved ultra-high throughput of 2.1Gbps and 2.4Gbps on the Xilinx Artix-7 FPGA and Kintex-7 FPGA, respectively, achieving efficient utilization of hardware resources. Compared with other architectures, this design has significant advantages in terms of throughput and resource utilization.

As the number of 3D-IC stacks increases, defects of through silicon via (TSV) in manufacturing and bonding process seriously affect the yield and reliability of the chip. Comparing to discarding these defective ones, some faulttolerant architectures are proposed, however, these existing schemes have great hardware overhead. In the paper, an N:1 single-channel time division multiple access (TDMA) faulttolerant technique using redundant TSV to tolerate TSV defect is proposed. Data is grouped and transmitted through TSV by TDMA mechanism, which reduces the number of TSV. The number of groups depends on bandwidth and hardware. The N: 1 single-channel TDMA structure is designed to use a single TSV to accomplish the time-sharing transmission of a group of signals. Each signal TSV is equipped with an additional TSV to improve the fault-tolerant coverage. The functions are verified on 40 nm Xilinx virtex-6 FPGA. The simulation results of Design Compiler based on 45 nm PTM show that the fault coverage rate can be increased to 100%, and the area overhead is reduced by 60.8% compared with the existing methods.

Since the physical defects such as resistive open and leakage in through silicon vias (TSVs) caused by immature manufacturing techniques tend to undermine the reliability and yield of 3-D integrated circuits, it is very important to test the TSV as early as possible in the fabrication process. There are some shortcomings in the existing prebond TSV test techniques, such as incomprehensive fault coverage, large area overhead, and additional test time. To overcome these problems, a noninvasive solution for prebond TSV test based on pulse shrinking is proposed in this paper. This method makes use of the fact that defects in TSV lead to variation in the propagation delay-the rise and fall times are first transformed into pulse width, and the pulse shrinking technique is used to digitize the pulse width into a digital code which is then compared with an expected value for a fault-free TSV. Experiments on defect detection are carried out using HSPICE simulations with realistic models for 45-nm CMOS technology. The results show that the proposed method performs better than the existing methods in terms of fault coverage, area overhead, and test time.

A new test vector compression/decompression scheme, namely a scheme of logic operation between adjacent bits (LOBAB) is presented, which is based on bitwise logic operation between itself and its previous bit. It turns all kinds of series including continuous series, such as a series of all 0s and all 1s, and reversal series, such as a series of 01 and 10, into series of all 0s by logic operation between adjacent bits. On one hand, the two kinds of series, continuous series and reversal series, are both taken into account, which decreases the number of division to the original test data. On the other hand, all series are turned into series of all 0s, which eases the process of encoding and decoding. Compared with other already known schemes this scheme has some characteristics, such as high compression ratio, easy control and implementation. The performance of the algorithm is mathematically analyzed and its merits are experimentally confirmed on the larger examples of the ISCAS89 benchmark circuits.

A novel test data compression coding scheme, block marking and updating coding, is proposed in this paper. Test data in the test set was divided into successive fixed-length vectors, called blocks, and then they were marked according to their compatibility compared with a reference vector. An operation that is similar to difference and a technique that strategically fills in don 't-care bits are combined to increase the probabilities of compatibility or inverse compatibility. It effectively compresses test data and its decompression structure is very simple. Experimental results of ISCAS-89 benchmark circuits show that the scheme is very effective.

In this paper, a BIST scheme based on selecting state generation of folding counters is presented. LFSR is used to encode the seeds of the folding counters, where folding distances (or indexes) are stored to control deterministic test patterns generation, so that the generated test set is completely equal to the original test set. This scheme solves compression of the deterministic test set and overcomes overlapping and redundancy of test patterns produced by the different seeds. Experimental results prove that it not only achieves higher test data compression ratio, but also efficiently reduces test application time, and that the average test application time is only four percent of that of the same type scheme.

A novel architecture based on mixed mode BIST for sharing among multiple logic cores on an system-on-a-chip is presented. In the architecture a single-polynomial LFSR with maximum degree in the multiple cores can be selected to generate pseudo-random patterns to cover the easy to detect faults for the all cores. For the remaining faults of the each core deterministic test patterns can be compressed by a two-dimensional compression scheme, where the LFSR encodes the seeds of a folding counter as the seeds of the LFSR so as to reduce amount of test data storage, and all of the cores under test can use the unique LFSR to decompress the encoded seeds. Experimental results indicate that the proposed scheme can achieve a significant amount of compression for test data storage, and the simple and flexible architecture can be directly embedded on chip for systems-on-a-chip test.