The authors point out that proper usage of regularity in digital systems leads to efficient as well as economical designs. This important question of regularity extraction is examined, and a general and efficient methodology for component clustering based on the concept of structural regularity is presented. While the concept of regularity can be employed to simplify many problems in the area of design automation, system- and logic-level applications are emphasized here. The authors show how identifying clusters in a circuit can simplify two important CAD problems-system-level clustering and module (layout) generation. A prototype system based on these ideas has been built, and some real-life examples are considered for testing. The results are encouraging; they demonstrate the essential role such a system could play in aiding the high-level system designer. Research is under way to explore some of the other promising applications that such a system could have.>

This paper presents an architectural synthesis approach for a widely used class of digital systems characterized by inherent regularity in their description. This approach relies on a novel modeling or abstraction of the problem domain to facilitate a hierarchical solution method. The modeling is based on exploiting the inherent regularity in the system description to cluster its behavioral operations. The method emphasizes prudent postponement of design decisions until enough physical design information is available to estimate layout effects like wiring; we use well-known area-delay estimators for this purpose. The approach has the advantage that it keeps track of a set of potentially good candidate solutions, rather than narrowing down to a single solution very early in the design process. Through an extensive set of experiments on well-known DSP design examples, we demonstrate the advantages that such distinctive features have to offer; the impact of hierarchy on several important issues, such as interconnection area, extent of design space explored, etc., is presented.>