This paper presents the design of a wideband pipelined multi-stage noise shaping (MASH) continuous time (CT) delta-sigma modulator (DSM). The quantization error of the overall$1^{\mathrm {st}}$-stage DSM is extracted as the input of the$2^{\mathrm {nd}}$stage, while the outputs of both stages are simply combined without using any digital filters. Overall, different shaping functions are generated for both QN without requiring any digital QN cancellation. Therefore, the pipelined MASH (PMASH) significantly mitigates QN leakage while retaining the decent loop stability of a traditional MASH. Additionally, several analyses have been made for the PMASH topology, e.g. the design guideline, the signal transfer function (STF), the robustness, etc. Clocked at 800MHz and enabling on-chip DAC calibration, the 65nm CMOS prototype with an exemplary 2-2 topology using multi-bit quantizers achieves 82.6 dB SNDR, 98.8 dB SFDR over 15.4 MHz BW at −0.5 dBFS 1.8 MHz input. The power consumption is 16.9 mW with 1.2V/1.5V supplies. It results in a competitive FoM${}_{\mathrm {S\vert SNDR}}$of 172.2 dB, while it avoids any off-chip calibrations.

Dynamic voltage and frequency scaling (DVFS) is commonly used for the balance of performance and power of mobile processors. Conventional DVFS regulators take the processor cores with the same power and performance weight showing their inability in the regulation of heterogeneous processors. This paper proposes a core-aware frequency-power evaluation scheme that utilizes a multilayer perceptron (MLP) to assess the efficacy of DVFS regulation actions. Additionally, a ResNet-based DVFS regulator, trained with the assistance of the MLP, is developed for heterogeneous multi-core processors. Evaluated on Xiaomi 13 Pro powered by a Qualcomm Snapdragon 8 Gen 2, the proposed DVFS approach achieves an up to ×1.47 improvement in FPS Performance Per Watt (FPPW) compared with the Qualcomm's default DVFS governor in video recording scenario.

Chiplet-based deep neural network (DNN) accelerator is a promising solution to balance the performance and manufacturing cost. However, different from monolithic chips, interconnect network design and architectural partitioning for multiple chiplets would result in a huge design space and make it difficult to keep scalability and high hardware utilization. Moreover, how to efficiently map DNN workloads onto multiple DRAM dies and compute dies is another major challenge. To alleviate the above issues, in this work, we propose INDM, a chiplet-based interconnect network and dataflow mapping co-optimization for DNN accelerators. First, we propose an efficient hierarchical interconnect network composed of a multiring on-die network and a cluster-based interdie network, to facilitate the data reuse and traffic pattern in DNN workloads. Second, architectural partitioning and topology exploration for chiplet-based DNN accelerators are proposed to find the optimal architecture configurations. Third, an interdie communication-aware dataflow mapping is proposed to minimize traffic congestion during DNN layer switching. We implement the proposed chiplet-based interconnect network design and dataflow mapping algorithm for a set of popular DNN models, including VGG-16, ResNet-18, DarkNet-19, ResNet-50, and ResNet-101. Experimental results show that as compared with the state-of-the-art related work, such as NN-Baton and SIMBA, our work achieves 26.00%–73.81% energy-delay-product (EDP) reduction and 26.93%–79.78% latency reduction.

Reinforcement learning (RL) based dynamic voltage and frequency scaling (DVFS) is an effective approach to balance performance and power consumption for video rendering applications. To approximate the “God’s eye view” regulation, the CPU-GPU should be fine-grained regulated and the SoC have to be fully observed by a RL-based DVFS governor. Fine-grained regulation with traditional value-based RL governor suffers action space explosion and it is impossible to have a fully observable SoC. To address these two issues, a governor based on deep recurrent deterministic gradient (DRDPG) governor is proposed. The governor is based on Deterministic Policy Gradient (DDPG) algorithm with embedded recurrent neural network (RNN). The DDPG algorithm guarantees fine-grained power regulation without action space explosion and the RNN-FC network topology mitigates the partial observability issue. Evaluated on the Nvidia Jetson NX platform, the proposed DRDPG governor achieves over 19% better regulation efficiency compared with Linux default governors and shows superior regulation efficiency to other RL-based state-of-the-arts. Implemented in a 55-nm CMOS process, the proposed governor draws merely 2.16-mA from a 1.2-V supply at 1-MHz clock occupying a silicon area of 0.075mm$^2$.

Wearable Internet of Things (IoT) devices are gaining ground for continuous physiological data acquisition and health monitoring. These physiological signals can be used for security applications to achieve continuous authentication and user convenience due to passive data acquisition. This paper investigates an electrocardiogram (ECG) based biometric user authentication system using features derived from the Convolutional Neural Network (CNN) and self-supervised contrastive learning. Contrastive learning enables us to use large unlabeled datasets to train the model and establish its generalizability. We propose approaches enabling the CNN encoder to extract appropriate features that distinguish the user from other subjects. When evaluated using the PTB ECG database with 290 subjects, the proposed technique achieved an authentication accuracy of 99.15%. To test its generalizability, we applied the model to two new datasets, the MIT-BIH Arrhythmia Database and the ECG-ID Database, achieving over 98.5% accuracy without any modifications. Furthermore, we show that repeating the authentication step three times can increase accuracy to nearly 100% for both PTBDB and ECGIDDB. This paper also presents model optimizations for embedded device deployment, which makes the system more relevant to real-world scenarios. To deploy our model in IoT edge sensors, we optimized the model complexity by applying quantization and pruning. The optimized model achieves 98.67% accuracy on PTBDB, with 0.48% accuracy loss and 62.6% CPU cycles compared to the unoptimized model. An accuracy-vs-time-complexity tradeoff analysis is performed, and results are presented for different optimization levels.

Unsupervised domain adaption (UDA), which aims to enhance the segmentation performance of deep models on unlabeled data, has recently drawn much attention. In this paper, we propose a novel UDA method (namely DLaST) for medical image segmentation via disentanglement learning and self-training. Disentanglement learning factorizes an image into domain-invariant anatomy and domain-specific modality components. To make the best of disentanglement learning, we propose a novel shape constraint to boost the adaptation performance. The self-training strategy further adaptively improves the segmentation performance of the model for the target domain through adversarial learning and pseudo label, which implicitly facilitates feature alignment in the anatomy space. Experimental results demonstrate that the proposed method outperforms the state-of-the-art UDA methods for medical image segmentation on three public datasets, i.e., a cardiac dataset, an abdominal dataset and a brain dataset. The code will be released soon.

With the advancement of artificial intelligence, the collaboration of multiple deep neural networks (DNNs) has been crucial to existing embedded systems and cloud systems, especially for automatic driving applications as well as augmented and virtual reality (AR/VR) applications. To trade off between cost and performance, chiplet-based DNN accelerators have emerged as a promising solution for accelerating DNN workloads. However, most existing mapping methods for multiple DNNs target for the monolithic chip, which fail to solve the problems faced by the emerging multi-chiplet architecture, such as the problems of distributed memory access, complex heterogeneous interconnect network, and the scaling-up of computing resources. In this work, we propose M2M, a fine-grained mapping framework for accelerating multiple DNNs on a multi-chiplet architecture. It includes a temporal and spatial task scheduling for reconfigurable dataflow accelerators and a communication-aware task mapping in a heterogeneous interconnect network. To enhance communication efficiency and reduce the overall latency, we further propose a fine-tuned quality-of-service (QoS) policy for network-on-package (NoP) links. To the best of our knowledge, this is the first fine-grained mapping framework for multiple DNNs on a multi-chiplet architecture. We implemented the proposed fine-grained mapping framework using genetic algorithm and simulated annealing algorithm. Experimental results show that our work achieves 7.18%–61.09% latency reduction under vision, language, and mixed workloads when compared with the state-of-the-art related work.

Two-step linear-exponential architectures can be applied to incremental ADCs (IADC) to achieve high resolution. In the first step, the ADC works as a normal first-order IADC while, in the second step, the exponential integrator is used to implement extended counting. There exist two architectures for the implementation of the exponential step, where the only difference depends on whether the input signal is connected or disconnected. By conducting a comparative analysis on such two slightly different linear-exponential architectures, we propose to combine the exponential and slope techniques to further boost the resolution without degrading its original thermal-noise suppression ability and DWA effectiveness. Mathematical analysis and simulation results are presented to confirm the principle of the proposed IADC.

This paper presents a low-power, low-noise, gain and bandwidth individually tunable analog front-end (AFE) for ExG signals. The proposed three-stage AFE with a bandwidth programmable amplifier enables individually tuning the bandpass cutoff frequencies in the range of 0.4 to 1.9kHz as well as the gain from 40 to 63dB. Designed in a$0.35 \mu\mathrm{m}$CMOS process with an area of 0.3mm2, the AFE achieves over 120dB CMRR with input referred noise of 516nVrms and a noise efficiency factor of 2.57. The chip consumes$2.5 \mu\mathrm{A}$at 1.8V supply.

This work introduces a two-channel time-interleaved (TI) continuous-time (CT) 3rd-order delta-sigma modulator (DSM). It uses the information from one complete channel to predict the other channel based on the extrapolation principle. Note that, Cascaded Integrator of Distributed Feedforward (CIFF) topology is selected for the loop filter for the following reasons: 1) it could reduce the number of required feedback DACs as much as possible; 2) it allows to implement the zero optimization for the TI DSM such that the performance could be further improved. Furthermore, we employ the technique of error correction to address the issue regarding the delay-free feedback path, which originates from the extrapolating TI DSM. We present the derivations of the target TI CT DSM starting from a single-channel discrete-time (DT) DSM, while the compensation for excess loop delay (ELD) is considered. Fabricated in 65nm CMOS process, this modulator achieves an equivalent output sampling rate of 800MS/s, while the analog channel operates at 400MHz. It exhibits a signal-to-noise and distortion ratio (SNDR) /spurious-free dynamic range (SFDR)/dynamic range (DR) of 75.5dB/89.7dB/79dB over a 10MHz bandwidth. The total power consumption is 33.73mW from 1.2v/1.8v power supplies. It results in a Schreier Figure of Merit (FoM) of 163.7dB based on DR.

This paper presents a continuous-time (CT) 0–4 dual-stage Multi-stAge Noise-sHaping (MASH) Delta-Sigma Modulator (DSM), exhibiting +5dBFS maximum stable amplitude (MSA). In the context of 0–4 MASH topology, the 4-bit CT DSM employed as the second stage only processes 4-bit quantization noise (QN) of the front-end. Though the input signal exceeds the full scale (FS), the second stage still stays stable as long as the signal leakage does not overload it. Such feature guarantees the improved stability over a wider signal input range. In addition, to address the well-known QN leakage issue of MASH topology, we propose to combine the feedforward topology with proportional-integral-based excess loop delay compensation. It ensures high robustness of the proposed 0–4 MASH DSM without requiring any calibration. Additionally, we present an analysis of the anti-aliasing filtering (AAF) for the 0-X MASH DSM. It is found that the overall AAF of the 0-X MASH DSM is contributed from the second stage. Sampled at 400MHz, the 65nm CMOS experimental prototype measures signal-to-noise and distortion ratio (SNDR)/spurious-free dynamic range (SFDR) of 76.7dB/87.3dB over a 10MHz bandwidth with 15.1mW power consumption. Moreover, with achieving +5dBFS MSA, the dynamic range (DR) is extended to be as high as 85dB, resulting in a state-of-the-art Scherier Figure of Merit (FoM) of 173.2dB based on DR.

Embedded arrhythmia classification is the first step towards heart diseases prevention in wearable applications. In this paper, a robust arrhythmia classification algorithm, NEO-CCNN, for wearables that can be implemented on a simple microcontroller is proposed. The NEO-CCNN algorithm not only detects QRS complex but also accurately locates R-peak with the help of the proposed adaptive time-dependent thresholding technique, improving the accuracy and sensitivity in arrhythmia classification. An optimized compact 1D-CNN network (CCNN) with 9,701 parameters is used for classification. A QRS complex augmentation method is introduced in the training process to cater for R-peak location error (RLE). A nested k1k2-fold cross-validation method is utilized to evaluate the robustness of the proposed algorithm. Simulation results show that the proposed algorithm has the ability to detect more than 99.79% of R peaks with an RLE of 7.94 ms for the MIT-BIH database. Implemented on the STM32F407 microcontroller, NEO-CNN attains a classification accuracy of 97.83% and sensitivity of 96.46% using only 8s window size.

The advancement of object detection algorithms makes them widely used in autonomous systems. However, due to high computational complexity of Convolutional Neural Networks(CNN), stringent latency requirement is hard to meet for real-time object detection. To address this problem, a low-latency accelerator architecture is proposed in this paper. A fine-grained column-based pipeline architecture with padding skip technique is implemented to reduce the start-up time of pipeline. In order to cut down the computational time of CNN, double signed-multiplication correcting circuit is introduced. In addition, pooling unit with share buffer is proposed to reduce storage cost for pooling layer. To demonstrate our new architecture, we implement the YOLOv2-tiny deep neural network (you-only-look-once) with input size 1280×384 on ZC706 development board, improving the latency by 2.125× to 2.34× compared to previous FPGA accelerator for YOLOv2-tiny.

For the problem of early detection of atrial fibrillation (AF) from electrocardiogram (ECG), it is difficult to capture subject-invariant discriminative features from ECG signals, due to the high variation in ECG morphology across subjects and the noise in ECG. In this paper, we propose an Discrete Biorthogonal Wavelet Transform (DBWT) Based Convolutional Neural Network (CNN) for AF detection, shortly called DBWT-AFNet. In DBWT-AFNet, rather than directly feeding ECG into CNN, DBWT is used to separate sub-signals in frequency band of heart beat from ECG, whose output is fed to CNN for AF diagnosis. Such sub-signals are better than the raw ECG for subject-invariant CNN representation learning because noisy information irrelevant to human beat has been largely filtered out. To strengthen the generalization ability of CNN to discover subject-invariant pattern in ECG, skip connection is exploited to propagate information well in neural network and channel attention is designed to adaptively highlight informative channel-wise features. Experiments show that the proposed DBWT-AFNet outperforms the state-of- the-art methods, especially for ECG segments classification across different subjects, where no data from testing subjects have been used in training.

In this demonstration, we present a non-invasive, real-time lung imaging system based on the electrical impedance tomography (EIT) technique. EIT is a medical imaging technique based on the electrical properties, i.e. resistivity and permittivity of tissues and organs. This demo is based on an EIT system-on-chip that utilizes frequency division multiplexing scheme to improve the throughput by 10, allowing clinicians to identify and prevent mechanical pulmonary injury during lung ventilation.

In this paper, we proposed an improved true random number generator (TRNG), which comprises a low-bias hardware random number generator (HRNG) and a scrambler based on linear-feedback shift register (LFSR). The HRNG reduces both DC offset from the noise sources and offset voltage from the comparator to generate low-bias bitstream. The LFSR-based scrambler further reduces the bias to zero without sacrificing the throughput rate. Randomness quality is verified by Monte Carlo simulations using the randomness test suite.

This paper presents a low power 3-lead ECG-on-Chip with real-time QRS detection and lossless data compression for wearable wireless ECG sensors. The proposed chip uses a novel approach that embeds the data compression in the heart beat (QRS) detection process leading to improved energy efficiency. The proposed technique achieves an average compression ratio (CR) of 2.15x and a peak detection sensitivity (Se) of 99.58% and positive productivity (+P) of 99.57%. The chip consumes only 960nW for QRS detection and data compression for 2-channel of ECG making it the lowest power chip.

Body channel communication (BCC) is one of the best candidates for communications in wireless body sensor networks as it uses the human body as transmission media to minimize transmission loss resulting better energy efficiency. The main issue of BCC is the loss in its backward path, which is formed by the capacitive coupling between two floated GND electrodes (GEs) of transmitter (TX) and receiver (RX). To mitigate the backward path loss, an off-chip inductor could be used to resonate with the backward capacitance to reduce the impedance of the backward path. However, this method is not suitable for wearable applications as the off-chip inductor only works for fixed communication distance. In this paper, we present a novel self-adaptive capacitive compensation (SACC) scheme to reduce the capacitive loss of the backward path. The proposed system automatically estimates the distance between GEs of TX and RX with the help of received signal strength indicator (RSSI). The backward capacitance is then calculated based on the estimated distance. And then the capacitance is compensated by a digitally controlled active inductor to reduce the backward path loss. Simulation shows that the proposed scheme achieves more than 15 dB channel enhancement at the IEEE 802.15.6 standard frequency.

The huge area overhead of the interconnect is one of the critical issues in static random access memory (SRAM)-based field-programmable gate arrays (FPGAs), resulting in high power consumption and slow operation speed. Another critical issue is the volatile feature of the SRAM, which leads to high standby leakage current and long power-ON time. Resistive random access memory (RRAM) with a high resistance ratio and zero standby power possesses great potential in the FPGA applications. The conventional RRAM-based nonvolatile FPGAs (NVFPGAs) may use one-transistor 2-RRAM (1T2R) storage element to replace the SRAM or the one RRAM (1R) cell to replace both nMOS switch and SRAM. However, those NVFPGA schemes may suffer from the issues of low reliability, high configuration power, and high active leakage power. In this paper, we propose a novel element [one-diode two-RRAM (1D2R) cells] to replace the nMOS switch and 6 Transistors (6T) SRAM. Meanwhile, the novel block structures of the logic block, connection block, switch block, and the FPGA architecture based on the 1D2R element are proposed. Compared with the conventional 1T2R-based NVFPGA, our novel structure could improve the operation speed by 53% with a 40.5% lower operation power. Compared with the conventional 1R-based NVFPGA, the proposed scheme could greatly reduce the write error rate by eight orders with more than 20 times lower write power.

A multicontext field-programmable gate array (FPGA) is a solution to achieve fast run-time reconfiguration. However, SRAM-based multicontext FPGAs still suffer from high leakage power during sleep, slow power-ON speed, and excessive large memory area. Racetrack memory is one of the most promising resistive nonvolatile memories, with the advantages of low power, high density, and high speed. In this paper, we propose two racetrack memory-based nonvolatile storage elements (NVSEs) for multicontext FPGAs. One is the shifting-based NVSE (type-1) with the advantages of high density and low power. The other one is the address-based NVSE (type-2) with the advantages of high context switching speed and low context switching power. The versatile place and route simulation results show that the type-1 NVSE-based eight-context FPGA reduces the area, critical path delay, and the power of the SRAM-based eight-context FPGA by more than 68.1%, 22.8%, and 13%, respectively. The proposed type-2 NVSE-based FPGAs allow the contexts to be switched 4.46 times faster than the type-1 NVSE-based FPGAs. Both designs improve the FPGA power-ON speed by more than a million times. Compared with the conventional racetrack memory-based lookup table (LUT), the proposed racetrack memory-based LUT may reduce the total power by more than 25%.

Human body communication (HBC) has significant advantage over wireless communication schemes in wireless body area networks (WBANs) in terms of power efficiency due to the high conductivity of human body. An accurate circuit model for transmission channel is necessary for optimizing the HBC transceiver performance. Conventional models achieve limited accuracy because of incomplete body tissue model or the use of tranmission-line at circuit level. In this paper, we proposed a comprehensive HBC circuit model which is based on 5 human-surface tissue layers representing the physiological characteristics of living tissues and the frequency dependence of their dielectric properties. Instead of using transmission-line, our model is based on lumped-element analysis, which is more accurate at the 21 MHz frequency band specified by the IEEE 802.15.6 HBC standard. We verified the proposed model by actual measurement on human body at various of communication distances. Experimental results show that the proposed model achieved the minimum error among all the modeling works, i.e., 1.80% minimum error and 2.24% maximal error at various communication distances.

This paper presents a mostly digital IR UWB transceiver operating in 0~960 MHz frequency range for low power wearable and implantable biomedical devices. The UWB transmitter adopts a carrier-less pulse generator with BPSK modulation, and achieves energy efficiency of 100 pJ/pulse. Intermittent operation is adopted by the receiver to save power which consumes about 600 μW at 1 Mbps. The timing window of data coming is provided by a SAR DLL, which could retime the receiver clock to synchronize with the received data. This transceiver is implemented in 0.35 μm CMOS process and occupies a core area smaller than 0.8 mm2.

Body channel communication (BCC) is a most power efficient way for communications among sensors in a wireless body-area network (WBAN). In BCC, the forward signal of the quasi-static field is conducted by the body surface, whereas the backward path is formed by the electrostatic coupling between the GND electrodes (GEs) of transmitter and receiver. As a result, the transmission loss is dominated by the backward path, which has high impedance due to small air capacitance between two compact GEs. Conventional backward path enhancement techniques make use of a large inductor to resonate with the air capacitance in order to reduce the impedance. Such approach is not suitable for integrated solution and not reconfigurable for varying communication distances. In this paper, we propose a novel active channel enhancer to compensate the loss in backward path, which is integratable and reconfigurable for variable distances and frequencies. Designed with 0.13 µm CMOS process, the proposed active enhancer improves the quasi-static coupling by more than 15 dB for a wide frequency band of 40 MHz–120 MHz compared to the 4 dB enhancement of conventional method; and the power consumption is only 0.6 mW.

The overall accuracy and linearity of a matching-limited successive-approximation-register analog-to-digital converter are primarily determined by its digital-to-analog converter's (DAC's) matching characteristics. As the resolution of the DAC increases, it is harder to achieve accurate capacitance ratios in the layout, which are affected by systematic and random mismatches. An ideal placement for the DAC array should try to minimize the systematic mismatches, followed by the random mismatch. This paper proposes a placement strategy, which incorporates a matrix-adjustment method for the DAC, and different placement techniques and weighting methods for the placements of active and dummy unit capacitors. The resulting placement addresses both systematic and random mismatches. We consider the following four systematic mismatches such as the first-order process gradients, the second-order lithographic errors, the proximity effects, the wiring complexity, and the asymmetrical fringing parasitics. The experimental results show that the placement strategy achieves smaller capacitance ratio mismatch and shorter computational runtime than those of existing works.

In this paper, an asynchronous analog-to-information conversion system is introduced for measuring the RR intervals of the electrocardiogram (ECG) signals. The system contains a modified level-crossing analog-to-digital converter and a novel algorithm for detecting the R-peaks from the level-crossing sampled data in a compressed volume of data. Simulated with MIT-BIH Arrhythmia Database, the proposed system delivers an average detection accuracy of 98.3%, a sensitivity of 98.89%, and a positive prediction of 99.4%. Synthesized in 0.13 μm CMOS technology with a 1.2 V supply voltage, the overall system consumes 622 nW with core area of 0.136 mm (2), which make it suitable for wearable wireless ECG sensors in body-sensor networks.

Spin-transfer-torque magnetoresistive random access memory (STT-MRAM) is an emerging type of nonvolatile memory with compelling advantages in endurability, scalability, speed, and energy consumption. As the process technology shrinks, STT-MRAM has limited sensing margin due to the decrease in supply voltage and increase in process variation. Furthermore, the relatively smaller resistance difference of two states in STT-MRAM poses challenges for its read/write circuit design to maintain an acceptable sensing margin. The proposed reference circuits optimization scheme solves the reference resistance distribution issue to maximize the sensing margin and minimize the read disturbance, with low power consumption. Simulation results show that the optimization scheme is able to significantly improve the read reliability with the presence of one or few cases of reference cell failure, thus it eliminates the requirement of additional circuits for failure detection of reference cell or referencing to neighboring blocks.

This paper presents a new average-8T write/read decoupled (A8T-WRD) SRAM architecture for low-power sub/near-threshold SRAM in power-constraint applications such as biomedical implants and autonomous sensor nodes. The proposed architecture consists of several novel concepts in dealing with issues in sub/near-threshold SRAM including: 1) the differential and data-independent-leakage read port that facilitates robust and faster read operation and alleviates issues in the half-selected cell (pseudo-write) while reducing the area compared to the conventional 8T cell and 2) the various configurations from 14T for a baseline cell to 6.5T for an area-efficient 16-bit cell. These configurations reduce the overall bitcell area and enable low operating voltage. Two memory blocks based on the proposed architecture at the size of 16 and 64 kb, respectively, are fabricated in 0.13-μm CMOS process. The 64 kb prototype has an active area of 0.512 mm2 which is 16% less than that of the conventional 8T-cell-based design. The chip is fully functional for the read operation with 260 mV at 245 kHz and 270 mV for the write operation at 1 MHz. It can hold data down to 170 mV where the standby power consumption is only 884 nW.

A new approach for designing power-efficient wireless ECG sensors based on level-crossing sampling and linear interpolation is presented in this paper. With the adoption of level-crossing sampling at sensor nodes, significant sampling rate reduction is achievable which lowers the power consumption of wireless transmitters. At sensor gateways, linear interpolation is applied to convert the non-uniform samples into uniform format to enable conventional uniform DSP. A linear interpolator for such a system is demonstrated using a 0.35μm CMOS process, which consumes 12.08μW under a 3.3-V supply.

An adaptive teaching strategy can be defined as an optimal instruction that effectively meets the individual needs and is conveyed toward a student's different aptitude i.e., intellectual abilities, personalities, and cognitive styles of learning. It is widely adopted in teaching students with disabilities. The adaptive teaching pedagogy exploits interactions between learners and educator and is one of the best strategies to meet the different learning styles of individual student. The adaptive teaching creates a teaching and learning environment that improves the learning efficiency. This paper presents an online adaptive tutoring system (ATS) that is aimed at alleviating some of the problems that are faced by large class teaching. The ATS represents a knowledge domain as a concept structure and models the student with Bayesian networks. Based on the Bayesian student model, the tutoring system provides individualized tutoring and instant feedback to each student. The system has been applied in teaching digital circuit design in the Department of Electrical and Computer Engineering of National University of Singapore. The survey conducted indicates the effectiveness of the proposed ATS-based teaching strategy.

A low-voltage fourth-order audio ΔΣ modulator is designed with a single-loop single-bit feedforward structure. A 2- tap FIR filter is inserted in the feedback loop to effectively attenuate the high frequency quantization noise, resulting 22% reduction in the maximum integration step of the first integrator and relaxing the slew rate requirement for the OTA to 9.5 V/μsec (diff). The summation of feedforward paths is embedded in a multi-input quantizer to minimize power and area. Implemented in a 0.13-μm CMOS technology and clocked at 4 MHz, the modulator achieves 87.0 dB SNDR and 91.8 dB DR for a 20-kHz signal bandwidth while consuming 99.7 μW from a 0.7-V supply.

In this paper, we propose a novel design of quasi-delay-insensitive dual-rail asynchronous adder working at subthreshold region using 0.13 mum standard CMOS technologies. Power Delay Product (PDP) as measure of merit is used for comparison with other recent published subthreshold adders. Low-power consumption, low PDP and high robustness are demonstrated.

New multiplication-free FIR digital filters are introduced to replace the masking filter in narrowband frequency response masking (NBFRM) based filter. The proposed filters not only significantly improve the computational efficiency of NBFRM filters but also minimize the increment of the group delays compared with existing NBFRM design techniques.

A non-uniformly spaced digital FIR filter bank has been proposed for QRS detection in wearable biomedical devices in Body Area Network (BAN) applications. The proposed filter bank is constructed based on frequency-response masking technique and employs two half-band filters as prototype filters, which leads to significant savings in terms of arithmetic operations. The introduction of non-uniformly spaced filter bank further enhances the detection accuracy especially in the BAN applications where motion artifacts are a major concern. Simulations show that the proposed algorithm correctly detects the QRS of both resting and exercising ECG, even under the presence of severe motion artifacts, baseline drift and large P/T waves.

In this paper, we propose a full-hardware context-based adaptive binary arithmetic coder (CABAC) encoder, which is the entropy coding tool adopted in the main and higher profiles of the video coding standard H.264/AVC. All CABAC coding features are implemented in hardware (HW), and different coding modes including rate-distortion optimization (RDO) are fully supported. An efficient memory access scheme is also proposed to reduce context RAM access frequency, context RAM size, and operation delay for RDO context state backup and restoration. Constant throughput of 1 bin per cycle is achieved in different coding configurations. The CABAC encoder is physically implemented in 0.13 mum process, and its post-layout simulation can be run at 328 MHz. The chip takes up 1.41 mm2, and dissipates 0.79 mW to support 720p60 HDTV real-time encoding in RDO-off mode. Compared to the state-of-the-art reference design, the most significant advantage of this design is that a full HW implementation of CABAC encoder is proposed, which minimizes the computation on the host processor and data transfer on the system bus. Power consumption is minimal compared to reference designs using the same technology.

In this paper, we propose a hardware Context-based Binary Arithmetic Coder (CABAC) targeting the main profile of H.264/AVC standard. The encoder fully supports different coding modes including RDO coding. An efficient memory access scheme is proposed and shown to reduce context memory access rate, context memory size, and RDO context state backup and restore operation delay. Coding throughput of 1 bin/cycle is achieved by pipelined structure. The encoder is physical implemented with 362 MHz clock frequency and power reduction technique is also utilized.

In this paper, we proposed computationally efficient filter structures based on the frequency response masking (FRM) technique for the synthesis of arbitrary bandwidth sharp FIR filters. A two-step masking approach is introduced in the new structures to further reduce the arithmetic operations in the overall filter compared to original FRM structure. It was shown, by means of examples, that additional 12% to 17% savings in terms of numbers of arithmetic operations are achievable for the new structures.

An ultra-low-power, low-noise sensor interface IC dedicated for bio-signal acquisition is presented in this paper. The proposed system architecture is optimized to achieve a better trade-off between power consumption and noise figure. A 0.05 ~ 200 Hz bandpass function is embedded within the front-end amplifier, and a wide bandwidth buffer is inserted between the front-end amplifier and ADC to facilitate a power-efficient interface. The system also includes an 11-bit SAR ADC with nonlinearity of less than plusmn0.7 LSB. The measured input-referred noise is 2.1 muV integrated across the pass-band, achieving noise efficiency factor of 2.9, and the power consumption for the overall system is 1.1 muW under 1 V supply.

Content-dependent watermarking (CDWM) has been proposed as a solution to overcome the potential estimation attack aiming to recover and remove the watermark from the host signal. It has also been used for the application of content authentication. In this work, we first present an analysis on why some prior work on CDWM pose potential security problems due to their inherent cryptographic weakness. With the aim of achieving cryptographic level of security, we then propose a novel CDWM scheme based on homomorphic encryption and dirty paper precoding. The general idea is to introduce a decryption module before watermark detection to create some nonlinearity and thereby inhibit conventional watermark attacks based on linear operations. We conclude this paper by bringing up some thoughts on the integration of watermarking and cryptography.

In this paper, we present two new computationally efficient frequency-response masking (FRM) filter structures that combine the well-known FRM technique and prefilter-equalizer approach. Several multiplication-free prefilters are introduced for the proposed FRM filter structures. We show, by means of an example, that the newly developed prefilter-equalizer based FRM structures yield as much as 32% reduction in terms of the number of arithmetic operations compared to the original FRM approach.

In our previous work (Li et al., 2006), we have presented unequal authenticity protection (UAP), the methodology of effective protecting multimedia stream transmitted over error-prone wireless networks. In this paper, we extend the previous analysis and consider integrating UAP into the joint source-channel coding (JSCC) framework to achieve optimization of end-to-end quality of media content. We further illustrate the effectiveness of this system using an implementation on progressive JPEG coder.

There have been increasing concerns about the security issues of wireless transmission of multimedia in recent years. Wireless networks, by their nature, are more vulnerable to external intrusions than wired ones. Many applications demand authenticating the integrity of multimedia content delivered wirelessly. In this work, we describe a framework for jointly coding and authenticating multimedia to be delivered over heterogeneous wireless networks. We firstly introduce a novel concept called unequal authenticity protection (UAP), which unequally allocate resources to achieve an optimal authentication result. We then consider integrating UAP with specific source and channel-coding models, to obtain optimal end-to-end quality by the means of joint source-channel-authentication analysis. Lastly, we present an implementation of the proposed joint coding and authentication system on a progressive JPEG coder. Experimental results demonstrate that the proposed approach is indeed able to achieve the desired authentication of multimedia over wireless networks

We propose in this paper a novel content-aware stream-level approach to authenticating multimedia data transmitted over wireless networks. The proposed approach is fundamentally different from conventional authentication methods and offers robust authentication for multimedia data in the presence of channel noise. The scheme is designed in such a way that it facilitates explicit capture and exploitation of channel condition as well as how the multimedia content is packetized and transmitted. The design allows the integration of authentication with the framework of joint source and channel coding (JSCC) to achieve adaptiveness to the content and efficient utilization of limited bandwidth. We have realized the proposed scheme through optimal resource allocation and authentication graph construction. Experiment results demonstrated the effectiveness of this novel approach

This paper presents a new notion of authenticating degraded multimedia content streamed over wireless networks - unequal authenticity protection (UAP). Multimedia content differs from other data in that the importance of different bits within a bitstream often varies. Therefore, given limited resources, a natural solution is to apply better authenticity protection to more important bits, and vice versa. In this paper, a quantitative relationship between the optimal authentication probability and the given resource budget is firstly derived, followed by a proposed authentication graph which realizes the idea of UAP. Simulation results further confirm the validity of the proposal.

A design and circuit implementation of a CMOS fourth-order continuous-time bandpass fs/4 sigma delta modulator is presented. The fully differential architecture of the modulator includes integrated LC resonators with active Q enhancement and return to zero, half return to zero latches to drive the feedback switched current source DACs. The modulator, designed for 0.18μm/1.8V 1P6M CMOS process occupies a total area of 1.8mm2 dissipating 290mW from a 1.8V power supply. At a sampling rate of 4GHz and a signal of 1GHz with 500kHz bandwidth, the circuit achieves a peak Signal-to-Noise and Distortion Ratio (SNDR) of 38dB. A CMOS implementation of the modulator provides the feasibility of integrating the following DSP circuits on the same chip in a RF receiver. This paper is aimed to provide a CMOS solution for RF signal of 1GHz range.

In this paper, we describe a scalable (i.e., lossy-to-lossless) watermarking scheme which overcomes the problem of non-invertible distortion introduced by the watermark signal. The scheme is based on a standardized scalable audio coder (R.S. Yu, et al, 2004) -as a result, the embedded watermark inherits the scalability of the audio coder. We elaborate how the scalability can be used to realize the recovery of the lossless audio signal after watermark embedding. The experimental results demonstrate the validity of the proposed watermarking scheme in terms of robustness, data expansion and perceptual quality.

In this paper, we present a scalable (i.e. lossy-to-lossless) watermark scheme based on a recently standardized scalable audio coder-AAZ (R.S. Yu, et al., 2004). The proposed framework enables the recovery of the original lossless audio after watermark embedding, and in the meanwhile, is able to make the watermark adaptive such that the watermark distortion to the lossy host audio is minimized. An encryption mechanism is further employed for restricting unauthorized access to lossless audio and watermark removal. Based on this framework, we elaborate its possible applications on high-quality audio archiving and streaming. Experimental results demonstrate the validity of our proposal.

In line with the recent call for technology on Image Based Authentication (IBA) in JPEG committee [1], we present a novel graphical password design in this paper. It rests on the human cognitive ability of association-based memorization to make the authentication more user-friendly, comparing with traditional textual password. Based on the principle of zero-knowledge proof protocol, we further improve our primary design to overcome the shoulder-surfing attack issue without adding any extra complexity into the authentication procedure. System performance analysis and comparisons are presented to support our proposals.

The performance of automatic speech recognition (ASR) system can be significantly enhanced with additional information from visual speech elements such as the movement of lips, tongue, and teeth, especially under noisy environment. In this paper, a novel approach for recognition of visual speech elements is presented. The approach makes use of adaptive boosting (AdaBoost) and hidden Markov models (HMMs) to build an AdaBoost-HMM classifier. The composite HMMs of the AdaBoost-HMM classifier are trained to cover different groups of training samples using the AdaBoost technique and the biased Baum-Welch training method. By combining the decisions of the component classifiers of the composite HMMs according to a novel probability synthesis rule, a more complex decision boundary is formulated than using the single HMM classifier. The method is applied to the recognition of the basic visual speech elements. Experimental results show that the AdaBoost-HMM classifier outperforms the traditional HMM classifier in accuracy, especially for visemes extracted from contexts.