Microelectronics design is often a labor-intensive process involving extensive simulations, fabrication, and testing, particularly in analog design, which demands a skilled workforce with specialized knowledge. Emerging computing paradigms, such as neuromorphic and probabilistic computing, aim to harness the analog characteristics of devices for significant performance improvements over traditional methods. This presents a unique codesign challenge across the design stack, encompassing analog, mixed-signal, and beyond-CMOS devices. In this work, we introduce AI-guided codesign automation techniques, for the design of novel devices and circuits tailored for these cutting-edge computing paradigms, facilitating innovative solutions and hardware-aware algorithms for next-generation heterogeneous architectures.

Neuromorphic computing is concerned with designing computer architectures inspired by the brain, with recent work focusing on platforms to efficiently execute large spiking neural networks (SNNs). Future designs are expected to improve their capabilities and performance by incorporating novel features, such as emerging neuromorphic devices and analog computation. There is, however, a lack of high-level performance estimation tools to evaluate the impact of such features at the architectural level, to evaluate architectural tradeoffs, and to aid with co-design and design-space exploration. Existing neuromorphic simulators either do not consider hardware performance, only model abstract SNN dynamics or are targeted to a single specific architecture. In this work, we propose SANA-FE, a novel simulator that can rapidly and accurately estimate performance and energy efficiency of different SNN-based designs. Our simulator uses a general and configurable architecture description format that can specify a wide range of neuromorphic designs. Using such an architecture description, SANA-FE simulates system activity when executing a given spiking application at an abstract time-step granularity, and it uses activity counts and per-activity performance metrics to estimate energy and latency for each time-step. We further show a calibration methodology and apply it to model performance of Intel’s Loihi platform. Results demonstrate that our simulator can predict Loihi’s energy and latency for three real-world applications, within 12% and 25%, respectively. We further model IBM’s TrueNorth architecture, simulating a random network over$20\times $faster than existing discrete-event-based TrueNorth simulators. Finally, we demonstrate SANA-FE’s design-space exploration capabilities by optimizing a Loihi baseline architecture for two application, reducing run-time by 21% while increasing dynamic energy usage by only 2%.

Neuromorphic computing uses brain-inspired concepts to accelerate and efficiently execute a wide range of applications, such as mimicking biological circuits, solving NPhard optimization problems and accelerating machine learning at the edge. In particular, neuromorphic architectures to efficiently execute Spiking Neural Networks (SNNs) have gained popularity. SNNs extend artificial neural networks (ANNs) by encoding information in time as either rates or delays between spiking events, shared between neurons via their weighted connections. SNN-based platforms are event-driven, resulting in naturally sparse, noise-tolerant and power-efficient computation. In this tutorial, we present the state-of-the-art in scalable digital and analog spiking neuromorphic system architectures, and discuss current research trends within the neuromorphic architecture field at the system level. We further introduce our SANA-FE tool for Simulation of Advanced Neuromorphic Architectures for Fast Exploration, which has been developed as part of a collaboration between the University of Texas at Austin and Sandia National Laboratories. SANA-FE allows for modeling and performance-power prediction of different spiking hardware architectures executing SNN applications to support rapid, early system-level design-space exploration, hardware-aware application development and system architecture co-design. The tutorial includes a hands-on component in which SANA-FE’s capabilities are demonstrated and used to perform system design and application mapping case studies.

A longstanding goal of neuromorphic computing is to develop novel computer architectures with a brain-like energy footprint. Still, key biological components such as dendrites are often overlooked. Instead, more compact scalable neuron models are favored for neuromorphic implementations. Here we present a novel neuroscience-inspired multiplicative circuit that uses shunting inhibition as the multiplicative mechanism in a CMOS dendrite circuit. We demonstrate an experimental implementation of our model on a 350-nm process field programmable analog array (FPAA) integrated circuit (IC), that exhibits shunting inhibition as a multiplicative process in neuromorphic circuits.