This paper presents a test data compression scheme that can be used to further improve compressions achieved by linear-feedback shift register (LFSR) reseeding. The proposed compression technique can be implemented with very low hardware overhead. The test data to be stored in the automatic test equipment (ATE) memory are much smaller than that for previously published schemes, and the number of test patterns that need to be generated is smaller than other weighted random pattern testing schemes. The proposed technique can be extended to generate test patterns that achieve high n-detection fault coverage. This technique compresses a regular 1-detection test cube set instead of an n-detection test cube set, which is typically n times larger. Hence, the volume of compressed test data for n-detection test is comparable to that for 1-detection test. Experimental results on a large industry design show that over 1600X compression is achievable by the proposed scheme with the test sequence length, which is comparable to that of highly compacted deterministic patterns. Experimental results on n -detection test show that test patterns generated by the proposed decompressor can achieve very high 5-detection stuck-at fault coverage and high compression for large benchmark circuits.

In this paper, a novel diagnosis method is proposed. The proposed technique uses machine learning techniques instead of traditional cause-effect and/or effect-cause analysis. The proposed technique has several advantages over traditional diagnosis methods, especially for volume diagnosis. In the proposed method, since the time consuming diagnosis process is reduced to merely evaluating several decision functions, run time complexity is much lower than traditional diagnosis methods. The proposed technique can provide not only high resolution diagnosis but also statistical data by classifying defective chips according to locations of their defects. Even with highly compressed output responses, the proposed diagnosis technique can correctly locate defect locations for most defective chips. The proposed technique correctly located defects for more than 90% (86%) defective chips at 50times (100times) output compaction. Run time for diagnosing a single simulated defect chip was only tens of milli-seconds.

This paper presents techniques to improve compressions by improving fault coverage that can be achieved by broadcast scan. Due to reconvergent gates that artificially occur in broadcast scan, broadcast scan fault coverage is often much lower than standard serial scan fault coverage. The proposed scan chain reordering technique improves broadcast scan fault coverage by minimizing the number of reconvergent gates and hence no or very small number of test patterns are required to be applied by standard serial scan to detect faults undetected by broadcast scan. This increases the overall compression ratio. To eliminate or minimize increase in routing overhead, the distance that each scan cell can be relocated by the scan chain reordering procedure is limited. Test points are inserted to further reduce correlation among outputs of scancells. The proposed scan chain reordering technique improved broadcast scan fault converge by up to 8.5%. Large fault coverage improvement was achieved by the proposed method, especially for circuits that suffer low broadcast scan fault coverage. Broadcast scan fault coverage for the largest two industrial designs was even higher than standard serial scan fault coverage.

This paper presents a scan-based DFT technique that uses limited number of enhanced scan cells to reduce volume of delay test patterns and improve delay fault coverage. The proposed method controls a small number of enhanced scan cells by the skewed-load approach and the rest of scan cells by the broadside approach. Inserting enhanced scan cells reduces test data volume and ATPG run time and improves delay fault coverage. Hardware overhead for the proposed method is very low. The scan inputs where enhanced scan cells are inserted are selected by gain functions, which consist of controllability costs and usefulness measures. A regular ATPG can be used to generate transition delay test patterns for the proposed method. Experimental results show that test data volume is reduced by up to 65% and fault coverage is improved by up to about 6%.

Hardware–Software (HW–SW) co-synthesis is one of the key steps in modern embedded system design. Generally, HW–SW co-synthesis is to optimally allocate processors, assign tasks to processors, and schedule the processing of tasks to achieve a good balance among performance, cost, power consumption, etc. Hence, it is a typical multi-objective optimization problem. In this paper, a new multi-objective HW–SW co-synthesis algorithm based on the quantum-inspired evolutionary algorithm (MQEAC) is proposed. MQEAC utilizes multiple quantum probability amplitude vectors to model the promising areas of solution space. Meanwhile, this paper presents a new crossover operator to accelerate the convergence to the Pareto front and introduces a PE slot-filling strategy to improve the efficiency of scheduling. Experimental results show that the proposed algorithm can solve the typical multi-objective co-synthesis problems effectively and efficiently.

This paper presents an efficient method to block unknown values for temporal compactors. The control signals for the blocking logic are generated by a linear feedback shift register (LFSR). Control patterns, which describe values required at the control signals of the blocking logic, are compressed by LFSR reseeding. The size of the control LFSR, which is determined by the number of specified bits in the most specified control pattern, is minimized by propagating only one fault effect for each fault and targeting the faults that are uniquely detected by each test pattern. The linear solver to find seeds of the LFSR intelligently chooses a solution such that the impact on test quality is minimal. Very high compression (over 230X) is achieved for benchmark and industrial circuits by the proposed method. Experimental results show that the sizes of control data for the proposed method are smaller than prior work and the runtime of the proposed method is several orders of magnitude smaller than that of prior work. Hardware overhead is very low.

This paper presents an efficient method to block unknowns for temporal compactors. The proposed blocking logic can reduce data volume required to control the blocking logic and increase the number of scan cells that are observed by temporal compactors. Control patterns, which specify values required at the control signals of the blocking logic, are compressed by linear feedback shift register reseeding. In this paper, the blocking logic gates for some scan chains that do not capture unknowns are bypassed. Since all scan cells in these scan chains can be observed without specifying the corresponding bits in control patterns, more scan cells are observed while a smaller number of bits are required to be specified. The seed size is further reduced by reducing the numbers of specified bits in the densely specified control patterns. The proposed method can always achieve the same fault coverage that can be achieved by directly observing scan chains without any output compaction. Experiments with large industrial designs clearly demonstrate that the proposed method is scalable to large circuits. Hardware overhead for the proposed unknown blocking scheme is very low.

In this paper, a technique that can efficiently reduce peak and average switching activity during test application is proposed. The proposed method does not require any specific clock tree construction, special scan cells, or scan chain reordering. Test cubes generated by any combinational ATPG can be processed by the proposed method to reduce peak and average switching activity without any capture violation. Switching activity during scan shift cycles is reduced by assigning identical values to adjacent scan inputs and switching activity during capture cycles is reduced by limiting the number of scan chains that capture responses. Hardware overhead for the proposed method is negligible. The peak transition is reduced by about 40% and average number of transitions is reduced by about 56-85%. This reduction in peak and average switching activity is achieved with no decrease in fault coverage.

This paper presents a test data compression scheme that can be used to further improve compressions achieved by LFSR reseeding. The proposed compression technique can be implemented with very low hardware overhead. Unlike most commercial test data compression tools, the proposed method requires no special ATPG that is customized for the proposed scheme and can be used to compress test patterns generated by any ATPG tool. The test data to be stored in the ATE memory are much smaller than that for previously published schemes and the number of test patterns that need to be generated is smaller than other weighted random pattern testing schemes. Experimental results on a large industry design show that over 1600X compression is achievable by the proposed scheme with the number of patterns comparable to that of highly compacted deterministic patterns.

This paper presents a new blocking logic to block unknowns for temporal compactors. The proposed blocking logic can reduce data volume required to control the blocking logic and also increase the number of scan cells that are observed by the temporal compactors. Control patterns, which describe values required at the control signals of the blocking logic, are compressed by LFSR reseeding. In this paper, the blocking logic gates for some groups of scan chains that do not capture unknowns are bypassed. Since all the scan cells in these scan chain groups are observed without specifying the corresponding bits in control patterns, fewer specified bits are required and more scan cells are observed. The seed size is further reduced by reducing numbers of specified bits in the densely specified control patterns. The proposed method can always achieve the same fault coverage that can be achieved by direct observation of scan chains. Experiments with large industrial designs clearly demonstrate that the proposed method is scalable to large circuits. Hardware overhead for the proposed blocking logic is very low

This paper presents a hybrid compaction scheme for test responses containing unknown values, which consists of a space compactor and an unknown-blocking Multiple Input Signature Registers (MISR). The proposed scheme guarantees no coverage loss for the modeled faults. The proposed hybrid scheme can also be tuned to observe any user- specified percentage of responses for controlling the coverage loss for un-modeled faults. The experimental results demonstrate that, in comparison with a space compactor or an unknown-blocking MISR alone, the hybrid compaction scheme achieves a lower coverage loss without demanding more test-data volume. In addition, we propose a quantitative approach to estimate the required percentage of observable responses for the proposed scheme, directly based on a test-quality metric of un-modeled faults.

This paper presents a test data compression scheme that combines weighted random pattern testing and LFSR reseeding. Test patterns generated by the proposed decompressor can achieve high n-detection fault coverage. The proposed technique computes weight sets from a set of test cubes that are generated by a traditional 1-detection ATPG tool. The computed weight sets are modified to achieve high ndetection fault coverage. The proposed decompressor can be implemented with low area overhead. Since the proposed technique requires no special ATPG that is customized for the proposed scheme, it can compress test patterns generated by any ATPG tool and generate test patterns from the compressed test data that achieve high n-detection fault coverage. Experimental results show that test patterns generated by the proposed decompressor can achieve very high 5- detection stuck-at fault coverage and high compression for large benchmark circuits

For a space compactor, degradation of fault detection capability caused by the masking effects from unknown values is much more serious than that caused by error masking (i.e. aliasing). In this paper, we first propose a mathematical framework to estimate the percentage of observable responses under unknown-induced masking for a space compactor. We further develop a prediction scheme which can correlate the percentage of observable responses with the modeled-fault coverage and with a n-detection metric for a given test set. As a result, the quality of a space compactor can be measured directly based on its test quality, instead of based on indirect metrics such as the number of tolerated unknowns or the aliasing probability. With the prediction scheme above, we propose a construction flow for space compactors to achieve the desired level of test quality while maximizing the compaction ratio.

The presence of unknown values in simulation is the great est barrier to effective test response compaction. For space compactors, some responses may not be observable due to the masking effect caused by unknown values. This paper reports on experiments conducted to evaluate the impact on the test quality of various percentages of observable responses for both modeled and un-modeledfaults.