This work presents a novel power distribution network (PDN) analysis using the emerging physics-informed neural network (PINNs) model. Different from conventional solver-based analysis, PINN allows rapid analysis and prediction while maintaining the physics compliance for high-fidelity analysis. An adaptive multi-objective training strategy is introduced, incorporating an interconnection matrix and layer labeling to accelerate convergence across complex PDN structures. An embedded workload vector and a transient modulator with linear superposition method extend the model’s applicability to a wide range of power scenarios. The developed method is applied to both chip-level PDN analysis and Chiplet 2.5-D chip-package co-analysis, showing high accuracy and fast runtime compared with conventional methods. The approach captures both steady-state IR droop and dynamic transient supply droop, including IR and L•di/dt noise from package and on-die PDN. Experiments on 2.5-D Chiplets with RISC-V processors and CNN accelerators show that the proposed PINN-based method achieves a 299x and 7x reduction in runtime compared to conventional EDA tools or prior work and saves up to 80% of training data than traditional neural networks models.

As generative AI such as ChatGPT rapidly evolves, the increasing incidence of data misconduct such as the proliferation of counterfeit news or unauthorized use of Large Language Models (LLMs) presents a significant challenge for consumers to obtain authentic information. While new watermarking schemes are recently being proposed to protect the intellectual property (IP) of LLM, the computation cost is unfortunately too high for the targeted real-time execution on local devices. In this work, a specialized hardware-efficient watermarking computing framework is proposed enabling model authentication at local devices. By employing the proposed hardware hashing for fast lookup and pruned bitonic sorting network acceleration, the developed architecture framework enables fast and efficient watermarking of LLM on the small local devices. The proposed architecture is evaluated on Xilinx XCZU15EG FPGA, demonstrating 30x computing speed-up, making this architecture highly suitable for integration into local mobile devices. The proposed algorithm to architecture codesign framework offers a practical solution to the immediate challenges posed by LLM misuse, providing a feasible hardware solution for Intellectual Property protection in the era of generative AI.

Tropical algebra solves complex problems with only sum and min/max operations replacing expensive multiplication and addition in linear algebra. Due to the low computing cost, tropical algebra has recently gained significant attention in a broad range of areas such as combinatorial optimization, scheduling, machine learning, etc. In this paper, we propose a generic hardware accelerator architecture for tropical algebra supporting a wide range of applications. Novel time-domain (TD) computing accelerators with special mapping, precision expansion and, unrolling techniques are proposed to further improve hardware efficiency. Test results on various tropical calculations including linear regression, dynamic programming, and neural network are shown to demonstrate an energy saving from 1.5X to 2.1X, latency saving from 2.6X to 5.2X, or an overall energy-delay-product (EDP) improvement from 3.9X-10.5X compared with conventional digital implementation manifesting the promise of the algebraic solution on low power edge devices.