Artur Jutman

EDBT 2026 Demo / reviewers in the wild / expert

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32ranked-venue papers

6as first author

4since 2021 · last 2026

0000-0002-2018-5589ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 31 · 6 first-author · 4 since 2021Software engineering, systems software and programming languages · 5 · 1 first-author · 1 since 2021

Year	Publication	Venue	Position
2026	NURSE: A Distributed Architecture for Runtime Fault Management in Processor Designs Ashwin Santhosh, Artur Jutman, Endri Kaja, Wolfgang Ecker, Maksim Jenihhin	ETS	2
2026	Scalable Reliability Assessment of Vision Transformers on Systolic Arrays via Fault Propagation Analysis Natalia Cherezova, Artur Jutman, Maksim Jenihhin	IOLTS	2
2026	Special Session: Reliability Assessment of DNN Models and Inference on Systolic Arrays Natalia Cherezova, Salvatore Pappalardo, Annachiara Ruospo, Bastien Deveautour, Lorenzo Fezza, Artur Jutman, Ernesto Sánchez 0001, Alberto Bosio, Matteo Sonza Reorda, Maksim Jenihhin	VTS	6
2025	European Test Symposium Teams: an Anniversary Snapshot abstract The IEEE European Test Symposium (ETS) has been facilitating progress in electronic systems testing since its launch in 1996. On the occasion of its 30th anniversary, this collaborative paper gathers sections by 21 ETS teams to outline their influential ideas and milestones. Each team’s section highlights historical perspective, current research, frameworks and projects as well as forward-looking research agendas in the area of electronic-based circuits and systems testing, reliability, safety, security and validation. This anniversary summary documents how research of various ETS teams, exemplifying the test community, has been evolving and transitioning from concepts to practical standards and Electronic Design Automation (EDA) tools and flows. This legacy is a strong base to drive the next generation of advances in electronic systems testing. Maksim Jenihhin, Jaan Raik, Artur Jutman, Natalia Cherezova, Raimund Ubar, Liviu Miclea, Szilárd Enyedi, Iulia Stefan, Ovidiu Stan, Cosmina Corches, Zebo Peng, Petru Eles, Rolf Drechsler, S. Eggersglüß, Görschwin Fey, Andreas Glowatz, Daniel Tille, Georges Gielen, Anthony Coyette, Wim Dobbelaere, Ronny Vanhooren, Po-Yao Chuang, Erik Jan Marinissen, Giorgio Di Natale, M. Barragan, Paolo Maistri, S. Mir, Vatajelu I. Vatajelu, Paolo Bernardi 0002, Stefano Di Carlo, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante, Haralampos-G. D. Stratigopoulos, M. K. Michael, Stelios Neophytou, Stavros Hadjitheophanous, Kyriakos Christou, M. Skitsas, Alberto Bosio, Bastien Deveautour, Patrick Girard 0001, Marcello Traiola, Arnaud Virazel, Fernando Santos 0001, Angeliki Kritikakou, Gioele Casagranda, Marzio Vallero, Flavio Vella, Paolo Rech, Letícia Maria Veiras Bolzani, Milos Krstic, Marko S. Andjelkovic, Fabian Vargas 0001, Grigor Tshagharyan, Gurgen Harutunyan, Valery A. Vardanian, Samvel K. Shoukourian, Yervant Zorian, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, Mottaqiallah Taouil, Moritz Fieback, Anteneh Gebregiorgis, Rajendra Bishnoi, Said Hamdioui, Abhijit Chatterjee, Anurup Saha, Suhasini Komarraju, K. Ma, Chandramouli N. Amarnath, Mehdi Baradaran Tahoori, Mahta Mayahinia, Maryam Rajabalipanah, Katayoon Basharkhah, N. Nosrati, Zahra Jahanpeima, Zainalabedin Navabi, Hans-Joachim Wunderlich, Sybille Hellebrand	ETS	3
2019	A new FPGA-based Detection Method for Spurious Variations in PCBA Power Distribution Network abstract Nowadays, increasing demand for High-Performance Systems produces significant growth in usage of Field Programmable Gate Arrays (FPGAs) for different applications thanks to their flexibility and high level of parallelism. Such systems rely on complex multi-layer Printed Circuit Board Assemblies (PCBA)with a few dozens of hidden layers, stacked microvias and high-density interconnects. Along with creating new test challenges, the increasing PCBA complexity elevates the criticality of defects in various subsystems. One of such sub-systems is a Power-Delivery-Network (PDN) with operating margin progressively reduced due to increasingly strict requirements of High-Performance applications. As a consequence, Marginal Defects and process variations in a PDN may create latent problems that will manifest in a particular condition thus compromising the overall system performance and causing malfunctions. In this paper we propose a new FPGA-based non-intrusive method to detect Marginal Defects in a PCBA PDN. The method is based on a monitoring circuit that measures signal delays caused by PDN variations and thus detects relevant anomalies. Additional ad-hoc PDN stress circuits have been developed to validate the measurement technique. Experimental results demonstrating the consistency of the proposed approach are obtained by comparing stress and non-stress scenarios. Sergei Odintsov, Ludovica Bozzoli, Corrado De Sio, Luca Sterpone, Artur Jutman	DDECS	5
2019	Post-Silicon Validation of IEEE 1687 Reconfigurable Scan Networks abstract The increasing number of embedded instruments used to perform test, monitoring, calibration and debug within a semiconductor device has called for a brand new standard-the IEEE 1687. Such a standard resorts to a reconfigurable scan network to provide efficient and flexible access to instruments and to handle complex structures. As it has to deliver reliable service, many approaches, both formal and simulation-based, have been proposed in the literature to perform test, diagnosis and verification of such networks. This paper focuses on the problem of post-silicon validation of a network, a problem that has not been adequately addressed, yet. We analyze the mismatches between the specification and its silicon implementation, and we propose a methodology to detect a subset of them by applying functional patterns and observing the length of the active scan path. Experimental results on ITC2016 benchmarks demonstrate that the proposed approach is broadly applicable, and able to generate very effective sequences. We also classify mismatches that cannot be targeted relying exclusively on the active scan path length information. Aleksa Damljanovic, Artur Jutman, Giovanni Squillero, Anton Tsertov	ETS	2
2019	Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL abstract A fundamental part of the new IEEE Std 1687 is the Instrument Connectivity Language (ICL), which allows for abstract description of the scan network. The big novelty if compared to legacy solutions like BSDL is the possibility of describing new topology-enabling elements such as the Scan-Muxes in a behavioural way which can be easily and efficiently exploited by Test Generation Tools to retarget instrument-level operations to top-level patterns. This means that for a given design, the Developer will have to write both the RTL and the ICL descriptions: to the author's best knowledge there is no automated tool to make the translation RTL to ICL. This methodology is error-prone due to the human factor, the difference in intent in the two descriptions and the syntactic and semantic complexity of the languages. Incoherence between ICL and RTL will result in retargeting errors, so it is fundamental to validate the equivalence between the two descriptions. This paper presents an automated methodology that starting from the ICL description is able to generate a set of RTL testbenches that can be simulated against the original RTL model to detect discrepancies and incoherence, and provides quantitative metrics in terms of code and functional coverage. Experimental results are reported on the set of ITC2016 set of benchmark networks. Aleksa Damljanovic, Artur Jutman, Michele Portolan, Ernesto Sánchez 0001, Giovanni Squillero, Anton Tsertov	ITC	2
2019	IEEE European Test Symposium (ETS) abstract This paper is dedicated to the IEEE European Test Symposium (ETS). It offers an overview of all the European Test Workshop and Symposium events, from its first edition in 1996 to the next edition in 2020. Stephan Eggersglüß, Said Hamdioui, Artur Jutman, Maria K. Michael, Jaan Raik, Matteo Sonza Reorda, Mehdi Baradaran Tahoori, Elena I. Vatajelu	ITC	3
2017	BASTION: Board and SoC test instrumentation for ageing and no failure found abstract This is an overview paper that motivates and describes performed work done in the European Commission funded research project BASTION, which focuses on two critical problems of modern electronics: the No-Fault-Found (NFF) and CMOS ageing. New defect classes contributing to NFF have been identified, including timing related faults (TRF) at board level and intermittent resistive faults (IRF) at IC level. BASTION has addressed the mechanisms of ageing and developed several techniques to improve the longevity of electronic products. Embedded Instrumentation, monitors, and IEEE 1687 standard for reconfigurable scan networks (RSN) are seen as an important leverage that helped mitigating the impact of the above listed problems by facilitating a low-latency, scalable online system health monitoring and error localization infrastructure as well as integration of all heterogeneous technologies into a homogeneous demonstration platform. This paper helps the reader to get a general overview of the work performed and provides a collection of references to publications where the respective research results are described in detail. Artur Jutman, Christophe Lotz, Erik Larsson, Matteo Sonza Reorda, Maksim Jenihhin, Jaan Raik, Hans G. Kerkhoff, Rene Krenz-Baath, Piet Engelke	DATE	1
2017	Marginal PCB assembly defect detection on DDR3/4 memory bus abstract A contemporary high-performance system board is a complex 3D object that may contain dozens of hidden layers, stacked microvias, high density interconnect, with all of the above not contributing to the ease of test and reliability. High-speed signals are normally fine-tuned or even calibrated to deliver pitch perfect timing even in the case of now-ubiquitous DDR3 memories. Today, data transmission rates on the board may be reaching multigigabit ranges on a single channel. Such defects like dewetting, cold solder, head-in-pillow, voiding/crack in micro-via or excessive solder voids may result in system performance issues, increased error rates, intermittent faults and other sporadic stability issues observed in certain operation modes, at certain workloads or manifesting in a seemingly stochastic manner. In this work, we present a methodology aiming at systematic discovery of marginal defects, timing related faults and stability issues in board assembly's DDR3/4 data bus as part of the end-of-line testing in volume production environment. The methodology presented in this paper is based on an extended DDR memory controller in which we have converted the bus calibration mechanism into a fine-grain diagnostic instrument, which instead of masking marginal discrepancies (the normal case) would unveil and report them. Sergei Odintsov, Artur Jutman, Sergei Devadze	ITC	2
2016	On coverage of timing related faults at board level abstract In this paper, we demonstrate a clear gap in board level test coverage under category of timing related faults (TRFs). Although there are techniques that are capable to detect TRFs, there is no fault coverage metrics to quantify the quality of these techniques. To do that, we propose an easy-to-implement interconnect-level fault model extension towards TRFs. This extension can be integrated into existing test coverage models providing additional information on coverage of timing-related faults. Artur Jutman, Igor Aleksejev, Sergei Devadze	ETS	1
2016	Designing reliable cyber-physical systems overview associated to the special session at FDL'16 abstract CPS, that consist of a cyber part – a computing system – and a physical part – the system in the physical environment – as well as the respective interfaces between those parts, are omnipresent in our daily lives. The application in the physical environment drives the overall requirements that must be respected when designing the computing system. Here, reliability is a core aspect where some of the most pressing design challenges are: monitoring failures throughout the computing system, determining the impact of failures on the application constraints, and ensuring correctness of the computing system with respect to application-driven requirements rooted in the physical environment. This paper provides an overview of techniques discussed in the special session to tackle these challenges throughout the stack of layers of the computing system while tightly coupling the design methodology to the physical requirements. Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon D. ter Braak, Sergei Devadze, Görschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Könighofer, Jan Malburg, Shiri Moran, Jaan Raik, Gerard K. Rauwerda, Heinz Riener, Franz Röck, Konstantin Shibin, Kim Sunesen, Jinbo Wan	FDL	8
2016	A suite of IEEE 1687 benchmark networks abstract The saturation of the IJTAG concept and its approval as the IEEE 1687 standard in 2014 has generated a wave of research activities and created demand for a set of appropriate and challenging benchmarks. This paper presents such a set developed by an industrial and academic consortium and constructed in a way that facilitates objective comparison of experimental results across research groups as well as represents challenging network examples exhaustively utilizing features and constructs defined by the standard. The suite is arranged in four comprehensive categories, each having its particular purpose and composition principles, as described in the paper. We have also made an analysis of limitations of previous popular and ad-hoc benchmark sets as these limitations majorly motivated our current action. The new public-domain benchmarks are distributed together with source files and documentation through the dedicated web site. Some of the previous research results on IEEE 1687 have been reapplied on the new benchmarks set, thus creating an important initial reference point for the research community. Anton Tsertov, Artur Jutman, Sergei Devadze, Matteo Sonza Reorda, Erik Larsson, Farrokh Ghani Zadegan, Riccardo Cantoro, Mehrdad Montazeri, Rene Krenz-Baath	ITC	2
2016	Optimization of Boundary Scan Tests Using FPGA-Based Efficient Scan Architectures Igor Aleksejev, Sergei Devadze, Artur Jutman, Konstantin Shibin	J. Electron. Test.	3
2015	No Fault Found: The root cause abstract No Trouble Found (NTF) has been discussed for several years [1]. An NTF occurs when a device fails at the board/system level and that failure cannot be confirm by the component supplier. There are several explanations for why NTFs occur, including: device complexity; inability to create system level hardware/software transactions which uncover hard to find defects; different environments during testing (power, thermal, noise). More recently a new concept, No Fault Found (NFF), has emerged. A NFF represents a defect which cannot be detected by any known means so far. The premise is that at some point the defect will be exposed - most likely at a customer site when the device is in a system. Given that we looking for a defect that we know nothing about and are theoretically undetectable it will be interesting to see what the panel has to say about the nature of these defects and how we intend to find them. Erik Larsson, Bill Eklow, Scott Davidsson, Robert C. Aitken, Artur Jutman, Christophe Lotz	VTS	5
2014	High Quality System Level Test and Diagnosis abstract This survey introduces into the common practices, current challenges and advanced techniques of high quality system level test and diagnosis. Specialized techniques and industrial standards of testing complex boards are introduced. The reuse for system test of design for test structures and test data developed at chip level is discussed, including the limitations and research challenges. Structural test methods have to be complemented by functional test methods. State-of-the-art and leading edge research for functional testing will be covered. Artur Jutman, Matteo Sonza Reorda, Hans-Joachim Wunderlich	ATS	1
2014	Design, Verification, and Application of IEEE 1687 abstract IEEE 1687 (IJTAG) has been developed to enable flexible and automated access to the increasing number of embedded instruments in today's integrated circuits. These instruments enable efficient post-silicon validation, debugging, wafer sort, package test, burn-in, bring-up and manufacturing test of printed circuit board assemblies, power-on self-test, and in-field test. Current paper presents an overview of challenges as well as selected examples in the following topics around IEEE 1687 networks: (1) design to efficiently access the embedded instruments, (2) verification to ensure correctness, and (3) fault management at functions performed in-field through the product's life time. Farrokh Ghani Zadegan, Erik Larsson, Artur Jutman, Sergei Devadze, Rene Krenz-Baath	ATS	3
2012	Re-using chip level DFT at board level abstract As chips are getting increasingly complex, there is no surprise to find more and more built-in DFX. This built-in DFT is obviously beneficial for chip/silicon DFX engineers; however, board/system level DFX engineers often have limited access to the build in DFX features. There is currently an increasing demand from board/system level DFX engineers to reuse chip/silicon DFX at board/system level. This special session will discuss: What chip access is needed for board-level for test and diagnosis? How to accomplish the access? Will IEEE P1687 and IEEE 1149.1 solve these problems? Xinli Gu, Jeff Rearick, Bill Eklow, Martin Keim, Artur Jutman, Krishnendu Chakrabarty, Erik Larsson	ETS	6
2012	Embedded synthetic instruments for Board-Level testing abstract The main purpose of this paper is to refine the benefits of the FPGA-based synthetic instrumentation concept (see Section 1) proposed by us earlier [1] as well as to provide some new experimental data based on real industrial designs to show the efficiency of our methodology (see Section 2). Artur Jutman, Sergei Devadze, Igor Aleksejev, Thomas Wenzel	ETS	1
2012	FPGA-based synthetic instrumentation for board test abstract This paper studies a new approach for board-level test based on synthesizable embedded instruments implemented on FPGA. This very recent methodology utilizes programmable logic devices (FPGA) that are usually available on modern PCBs to a large extent. The purpose of an embedded instrument is to carry out a vast portion of test application related procedures, perform measurement and configuration of system components thus minimizing the usage of external test equipment. By replacing traditional test and measurement equipment with embedded synthetic instruments it is possible not only to achieve the significant reduction of test costs but also facilitate high-speed and at-speed testing. We detail the motivation and classify the FPGA-based instrumentation into different categories based on the implementation and application domains. Experimental results show the efficiency of this approach. Igor Aleksejev, Artur Jutman, Sergei Devadze, Sergei Odintsov, Thomas Wenzel	ITC	2
2011	Automatic SoC Level Test Path Synthesis Based on Partial Functional Models abstract While system level test was a topic of extremely high interest during the last decades, the cost of the test program development was continuously growing. The restricted capabilities of Boundary Scan (BS) with respect of such modern challenges as dynamic (timing-accurate), at-speed and high speed testing as well as in-system diagnosis of functional failures create considerable troubles for test engineers in production environments. In this paper, we propose a general modeling methodology for automatic test path synthesis for microprocessor SoC-based systems, that drastically reduces the cost of the test program. The new automation methodology forms a complementary solution to traditional boundary scan by overcoming its weaknesses at no investment into system design process. Anton Tsertov, Raimund Ubar, Artur Jutman, Sergei Devadze	Asian Test Symposium	3
2011	SoC and Board Modeling for Processor-Centric Board Testing abstract Many contemporary electronic systems are based on System-on-Chips (SoC) such as micro-controllers or signal processors that communicate with many peripheral devices on the system board and beyond. While, SoC test was a topic of extremely high interest during the last decade, the test beyond SoCs didn't get much attention after introduction of Boundary Scan (BS) 30 years ago. It is not a surprise that the restricted capabilities of BS with respect of such modern challenges as dynamic (timing-accurate), at-speed and high-speed testing as well as in-system programming create considerable troubles for test engineers in production environments. In this paper, we point out particular challenges in testing the system's infrastructure beyond the SoCs as well as propose a general modeling methodology for test automation for microprocessor SoC-based system boards. The new so-called "Lego-style" test automation methodology forms a complimentary solution to traditional boundary scan. Together, they provide extended fault coverage that targets shorts, opens, stuck-at faults as well as dynamic faults (e.g. delays and transition faults). The "Legostyle" model allows reducing the labour effort drastically once the library of model components is created. Anton Tsertov, Raimund Ubar, Artur Jutman, Sergei Devadze	DSD	3
2010	Parallel X-fault simulation with critical path tracing technique abstract In this paper, a new very fast fault simulation method to handle the X-fault model is proposed. The method is based on a two-phase procedure. In the first phase, a parallel exact critical path fault tracing is used to determine all the detected stuck-at faults in the circuit, and in the second phase a postprocess is launched which will determine the detectability of X-faults. Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman	DATE	4
2010	Structurally Synthesized Multiple Input BDDs for Speeding Up Logic-Level Simulation of Digital Circuits abstract Logic simulation is a critical component of the design tool flow in modern hardware development efforts. In this paper a new algorithm for parallel logic simulation is proposed based on a new model of Structurally Synthesized Multiple Input BDDs (SSMIBDD). The SSMIBDDs allow further model size reduction and therefore higher speed of logic simulation than its predecessor SSBDD model. The paper presents a method of SSMIBDD synthesis from the given gate network and the main principles of parallel logic simulation with SSMIBDDs. Experimental data demonstrate in average 2.9 times improvement in the speed of logic simulation because of the reduced number of nodes in SSMIBDDs. Similarly to the SSBDDs, the new model preserves structural information about the circuit, which is needed for processing of faults. The reduced complexity of SSMIBDDs leads to the more powerful fault collapsing and as the result to more efficient fault simulation and fault injection to evaluate the dependability of fault tolerant circuits. Dmitri Mironov, Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman	DSD	5
2010	Fault collapsing with linear complexity in digital circuits abstract The paper presents a new structural fault-independent fault collapsing method for test generation based on the topology analysis of the circuit, which has linear complexity. Fault collapsing is carried out by superposition of binary decision diagrams (BDD) for logic gates, which is used for constructing structurally synthesized BDDs (SSBDD). A new class of SSBDDs with multiple inputs (SSMIBDD) is proposed to reduce the size of collapsed fault sets. Experimental data show that the fault collapsing by the proposed method is more efficient than other strucural fault collapsing methods with comparative time cost are. Raimund Ubar, Dmitri Mironov, Jaan Raik, Artur Jutman	ISCAS	4
2009	Fast extended test access via JTAG and FPGAs abstract This paper describes a new test access protocol for system-level testing of printed circuit boards for manufacturing defects. We show that the protocol can be based on standard boundary scan (BS) instructions and test access mechanism (TAM). It means that the methodology does not require any changes/redesign of hardware and can be immediately implemented in the electronic manufacturing. Our solution needs however a proper software support and availability of programmable devices (FPGAs, CPLDs, etc.) on the board under test. The new technique dramatically extends the applicability of BS testing in the reality of modern complex on-board data transfer buses and protocols. Potentially, it can also increase the speed of in-system programming of flash memories and other tasks that are traditionally performed using BS. Sergei Devadze, Artur Jutman, Igor Aleksejev, Raimund Ubar	ITC	2
2008	Parallel fault backtracing for calculation of fault coverage abstract A new improved method for calculation of fault coverage with parallel fault backtracing in combinational circuits is proposed. The method is based on structurally synthesized BDDs (SSBDD) which represent gate-level circuits at higher, macro level where macros represent subnetworks of gates. A topological analysis is carried out to generate an efficient optimized model for backtracing of faults to minimize the repeated calculations because of the reconvergent fanouts. The algorithm is equivalent to exact critical path tracing, however, processing the backtrace in parallel for a group of test patterns. Because of the parallelism, higher abstraction level modeling, and optimization of the topological model, the speed of fault simulation was considerably increased. Compared to the state-of-the-art commercial fault simulators the gain in speed was several times. Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman	ASP-DAC	4
2007	Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs abstract An efficient method of parallel fault simulation for combinational circuits is proposed. The method is based on structurally synthesized BDDs (SSBDD) which represent gate-level circuits at higher, macro level where macros represent subnetworks of gates. Converting gate-level circuits to the macro-level is accompanied with fault collapsing. A parallel fault analysis algorithm for SSBDDs was developed. For the faults at fanout stems a new full Boolean differential based parallel fault analysis method is proposed. The algorithm is equivalent to exact critical path tracing. Because of the parallelism and higher abstraction level modeling the speed of analysis is considerably increased. Experimental data show that by the new method speed-up measured in several times has been achieved compared to the current state-of-the-art commercial tools and other exact critical path tracing methods. Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman	ETS	4
2006	Off-Line Testing of Delay Faults in NoC Interconnects abstract Testing of high density SoCs operating at high clock speeds is an important but difficult problem. Many faults, like delay faults, in such sub-micron chips may only appear when the chip works at normal operating speed. In this paper, we propose a methodology for at-speed testing of delay faults in links connecting two distinct clock domains in a SoC. We give an analytical analysis about the efficiency of this method. We also propose a simple digital hardware structure for the receiver end of the link under test to detect delay faults. It is possible to extend our method to combine it with functional testing of the link and adapt it for online testing Tomas Bengtsson, Artur Jutman, Shashi Kumar, Raimund Ubar, Zebo Peng	DSD	2
2005	An Educational Environment for Digital Testing: Hardware, Tools, and Web-Based Runtime Platform abstract We describe a new e-learning environment and a runtime platform for educational tools on digital system testing and design for testability. This environment is being developed in Tallinn University of Technology and consists of several functional layers. The first one is the hardware component used for illustration of various physical phenomena appearing in defected circuits. In many cases such phenomena are hard to illustrate by software simulation or by any other means, which makes the usage of such a hardware component unavoidable. The second component is a set of university tools covering a large scope of topics in basics of testing, diagnosis, and BIST. The tools represent an efficient alternative to hard-to-learn and expensive commercial CAD systems. The wrapper to these two components is a cross-platform Web interface that represents a server-based solution for using all the available tools and the hardware over Internet. The whole platform is an extendable server-based low-cost solution, which is easy to set-up and use. The learning environment is complemented by laboratory work scenarios and teaching materials that also available in the Web. Artur Jutman, Jaan Raik, Raimund Ubar, V. Vislogubov	DSD	1
2004	At-speed on-chip diagnosis of board-level interconnect faults abstract This article describes a novel approach to fault diagnosis suitable for at-speed testing of board-level interconnect faults.This approach is based on a new parallel test pattern generator and a specifically fault detecting sequence. The test sequence has tree major advantages.At first, it detects both static and dynamic faults upon interconnects. Secondly, it allows precise on-chp at-speed fault diagnosis of interconnect faults.Third, the hardware implementation of both the test generator and the response analyzer is very efficient in terms of silicon area. Artur Jutman	ETS	1
2001	Timing simulation of digital circuits with binary decision diagrams abstract Meeting timing requirements is an important constraint imposed on highly integrated circuits, and the verification of timing of a circuit before manufacturing is one of the critical tasks to be solved by CAD tools. In this paper, a new approach and the implementation of several algorithms to speed up gate-level timing simulation are proposed where, instead of gate delays, path delays for tree-like subcircuits (macros) are used. Therefore timing waveforms are calculated not for all internal nodes of the gate-level circuit but only for outputs of macros. The macros are represented by structurally synthesized binary decision diagrams (SSBDD) which enable a fast computation of delays for macros. The new approach to speed up the timing simulation is supported by encouraging experimental results. Raimund Ubar, Artur Jutman, Zebo Peng	DATE	2