Conventional magnetic nonvolatile-static random access memory (MNV-SRAM) suffers from large store current, which leads to low area and energy efficiency, severely limiting their development and application. This paper proposes a 10T-2MTJ NV-SRAM cell based on the in-plane voltage-gated spin-orbit torque magnetic tunnel junction (VGSOT-MTJ), which enables field-free deterministic magnetization switching and reduces the required store current by leveraging the voltage-controlled magnetic anisotropy (VCMA) effect to assist the store operation. Thereby, the proposed design achieves the smallest SRAM cell area compared to prior works, due to the relaxed transistor drive strength requirement. On the other hand, existing NV-SRAM restore schemes exhibit a substantial deterioration in restore error ratio (RSER) with increasing MTJ resistance. Targeting the high resistance characteristics of VGSOT-MTJ, we innovatively propose a pre-charge restore scheme with sensitive transistor isolation. Simulation results demonstrate that the proposed design achieves the lowest read and write energy in SRAM mode, with store energy 1.58× to 2.48× lower than other in-plane MTJ-based designs. And the proposed restore scheme significantly improves restore reliability with over 98.7% RSER enhancement, and shows superior robustness across different MTJ resistances and tunnel magnetoresistance ratio (TMR) conditions.

Runlength limited (RLL) codes are used in magnetic recording. The error patterns that occur with peak detection magnetic recording systems when using a runlength-limited code consist of both symmetric errors and shift errors. We refer to shift errors and symmetric errors collectively as mixed type errors. A method of providing error control for mixed type errors that occur in a runlength limited code comprised of (d, k) constrained sequences is examined. The coding scheme is to choose parity blocks to insert in the constrained information sequence. The parity blocks are chosen to satisfy the constraints and to provide some error control. The cases of single error-detection and single error-correction are investigated, where the single error is allowed to be a shift error or a symmetric error. Bounds are discussed on the possible lengths for the parity blocks. It is shown that the single error-detection codes are the best possible in terms of the length of the parity blocks.