Kyokko is an open, vendor-independent implementation of Xilinx's Aurora 64b66b protocol. It provides the interoperability of both Xilinx and Intel FPGAs over high-speed serial links such as optical, coaxial, or SFP cables. Currently, it works on Kintex, Virtex, Cyclone, and Arria FPGAs with less resource requirements and latency than Xilinx's Aurora 64b66b core. We'll make an on-line demonstration of connectivity among these FPGAs.

Fast Aerodynamics Routines (FaSTAR) is one of the most recent fluid dynamics software package. The problem of FaSTAR is hard to be executed in parallel machines because of its irregular and unpredictable data structure. Exploiting reconfigurable hardware with their advantages to make up for the inadequacy of the existing high performance computers had gradually become the solutions. However, a single FPGA is not enough for the FaSTAR package because the whole module is very large. Instead of using many FPGAs, partially reconfigurable hardware available in recent FPGAs is explored for this application. Advection term computation module in FaSTAR is chosen as a target subroutine. We proposed a reconfigurable flux calculation scheme using partial reconfiguration technique to save hardware resources to fit in a single FPGA. We developed flux computational module and five flux calculation schemes are implemented as reconfigurable modules. This implementation has advantages of up to 62.75% resource saving and enhancing the configuration speed by 6.28 times. Performance evaluation also shows that 2.65 times acceleration is achieved compared to Intel Core 2 Duo at 2.4 GHz.

FaSTAR developed by JAXA is a leading edge CFD (Computational Fluid Dynamics) program package which supports various solvers based on unstructured grids. The computation based on unstructured grid causes a lot of pipeline stalls by RAW (Read After Write) hazard when reconfigurable accelerators are implemented in FPGAs. In order to cope with this problem, the OoO (Out-of-Order) mechanism generator is proposed. By setting parameters depending on the target computation, the OoO mechanism with appropriate structure of the execution unit and waiting buffer is generated. The OoO mechanisms are applied to five subroutines in FaSTAR, and it achieved 2.6 times performance as the case of in-order execution, and 2.9 times as the software executed by Intel Core2Duo processor with reasonable amount of overhead.

The widespread use of ICT equipment is expected to increase the power consumed by ICT rapidly and it is recognized that the energy consumption of ICT equipment themselves (Green of ICT) should be one of key issues. This paper first identifies the need of the collaboration among end systems, the communication network and the power network, in order to reduce the total power consumption by the entire ICT systems. Next, this paper proposes the fundamental policies for the collaboration. One of them is to take any action to keep or put end systems or network devices in the sleep mode as much as possible when all areas have enough amount of available electric power, and to aggregate end systems and network devices in the area which has a largest amount of electric power capacity when multiple areas don't have enough amount of available electric power. Then, it is proposed to estimate the energy consumption of end systems by measuring and analyzing packets transferred in the network, in order to eliminate the processing load for information exchanges required for the collaboration among end systems and the network.

Resource reduction design techniques play an important role to implement large-scale FPGA-based accelerator systems in floating point applications since available resources on FPGAs are limited. This paper proposes a dataflow graph classification method which makes groups of graphs based on their similarity in order to bring out efficient graph combining. Aiming at finding effective parameters for the k-means algorithm, various parameter combinations are evaluated and compared in terms of resource reduction effects and performance. The experimental results using an FPGA-based biochemical simulator reveal that the graph clustering that uses information on the maximum common subgraphs achieve 73.3% of resource reduction rate while alleviating the performance degradation.

CFD is taken notice as a cost effective design tool for aircraft components. UPACS is a convenient CFD platform, since it supports a large degree of versatility using various kinds of solvers. However, its major drawback is a long simulation time. We have developed a UPACS accelerator named FLOPS-2D with multiple FPGA boards, and implemented some core functions. Here, by using flexibility of FPGAs, the selectable functions are proposed. All possible flux limiter functions in MUSCLs are implemented independently, and only required functions are selected and implemented with other modules to form the optimal structure. All implemented functions achieved at least 24 times higher performance than that with the Core 2 Duo, and configurable solvers using a desired flux limiter function and the number of arithmetic pipelines are developed.

One of the obvious advantages of FPGA-based reconfigurable computing is customizability of a tradeoff point between performance and hardware costs. However, this tradeoff has rarely been discussed in a whole application level, which is the most important view for application users. This paper presents empirical evaluation of a hardware module sharing technique which can shift a tradeoff point of area and performance on an FPGA-based biochemical simulator. The biochemical simulation results are discussed in terms of hardware costs, simulation throughput, parallelism extracted in simulation hardware, and data transfer overheads.

MOTIVATION: The accurate detection of orthologous segments (also referred to as syntenic segments) plays a key role in comparative genomics, as it is useful for inferring genome rearrangement scenarios and computing whole-genome alignments. Although a number of algorithms for detecting orthologous segments have been proposed, none of them contain a framework for optimizing their parameter values. METHODS: In the present study, we propose an algorithm, named OSfinder (Orthologous Segment finder), which uses a novel scoring scheme based on stochastic models. OSfinder takes as input the positions of short homologous regions (also referred to as anchors) and explicitly discriminates orthologous anchors from non-orthologous anchors by using Markov chain models which represent respective geometric distributions of lengths of orthologous and non-orthologous anchors. Such stochastic modeling makes it possible to optimize parameter values by maximizing the likelihood of the input dataset, and to automate the setting of the optimal parameter values. RESULTS: We validated the accuracies of orthology-mapping algorithms on the basis of their consistency with the orthology annotation of genes. Our evaluation tests using mammalian and bacterial genomes demonstrated that OSfinder shows higher accuracy than previous algorithms. AVAILABILITY: The OSfinder software was implemented as a C++ program. The software is freely available at http://osfinder.dna.bio.keio.ac.jp under the GNU General Public License. SUPPLEMENTARY INFORMATION: Supplementary data are available at Bioinformatics online.

Bioinformatics 25(7), 853–860. The publishers regret that there was an error in the corresponding author displayed. The corresponding author of this article is Yasubumi Sakakibara rather than Tsuyoshi Hachiya. The author group should have read: Tsuyoshi Hachiya1, Yasunori Osana2, Kris Popendorf1 and Yasubumi Sakakibara1,*

Stochastic simulation of biochemical reaction networks are widely focused by life scientists to represent stochastic behaviors in cellular processes. Stochastic algorithm has loop-and thread-level parallelism, and it is suitable for running on application specific hardware to achieve high performance with low cost. We have implemented and evaluated the FPGA-based stochastic simulator according to theoretical research of the algorithm. This paper introduces an improved architecture for accelerating a stochastic simulation algorithm called the Next Reaction Method. This new architecture has scalability to various size of FPGA. As the result with a middle-range FPGA, 5.38 times higher throughput was obtained compared to software running on a Core 2 Quad Q6600 2.40GHz.

Computational Fluid Dynamics (CFD) is an important tool for aeronautical engineers. Instead of expensive super-computers or clusters, using custom pipelines built on FPGAs is expected to be a cost effective solution to accelerate CFD. The problem is that to keep the pipeline busy is difficult because of the memory bandwidth. To deal with this problem, an effective memory access method using Block-RAMs is implemented based on a careful survey about memory access pattern. This work is targetting on two major subroutines in UPACS, a CFD software package. As a result, the amount of data transfer is reduced about 40%. This shows 46–170fold speed-up is expected by several Virtex-4 FPGAs compared to Itanium2 processor.

In order to simulate large scale biological models with a reconfigurable FPGA-based biochemical simulator system, reduction of required resources are essential. This paper proposes a method which combines common terms in rate law functions appeared in biochemical models and generates a shared hardware module used for numerical integration. In this approach, two functions are combined in a tree structure level, followed by pipeline scheduling and arithmetic module binding. The evaluation result reveals that this approach reduces hardware resources by 31.4% on average at the cost of 14.4% throughput degradation.

This paper introduces a scalable FPGA implementation of a stochastic simulation algorithm (SSA) called the Next Reaction Method. There are some hardware approaches of SSAs that obtained high-throughput on reconfigurable devices such as FPGAs, but these works lacked in scalability. The design of this work can accommodate to the increasing size of target biochemical models, or to make use of increasing capacity of FPGAs. Interconnection network between arithmetic circuits and multiple simulation circuits aims to perform a data-driven multi-threading simulation. Approximately 8 times speedup was obtained compared to an excution on Xeon 2.80GHz.

This paper studies several designs of network-based FPGA implementation of a stochastic simulation algorithm called the next reaction method, known for its large number of calculation involved. The procedure is divided into several subdivisions which will be implemented as independent modules, and they are connected with configurable interconnection networks so as to provide high throughput. By performing a multi-threading simulation, 3.6 times speedup was obtained compared with an execution on general purpose processors.

ReCSiP is an FPGA-based biochemical simulator to accelerate kinetic simulations of biochemical pathways. Biochemical models are described as a set of ordinary differential equations (ODEs). Each equation in the model is called "rate law function", which represents the velocity of corresponding biochemical reaction mechanism. ReCSiP achieves high-throughput simulation with statically pipelined rate law function modules and numerical integration modules on an FPGA. This paper shows the basic structure of ReCSiP, and results of evaluation in 2 aspects: area and throughput. As the summary of evaluation, 1) about 64% of the total circuit area is occupied by floating-point arithmetic units, and 2) with an XC2VP70, ReCSiP at 90MHz can achieve 20times or more speedup compared to Intel's Pentium4 microprocessor at 3.2GHz

Stochastic simulation of biochemical systems has become one of major approaches to study life processes as system, yet is a computational challenge to run the simulation due to its vast calculation cost. This paper shows the implementation and evaluation of a stochastic simulation algorithm (SSA) called "first reaction method" on an FPGA-based biochemical simulator. It achieves high throughput by (1) consecutively throwing data into deeply-pipelined floating point arithmetic units, and (2) by distributing multiple simulators for parallel execution. As the result of evaluation on an FPGA-based simulation platform called ReC-SiP2, the simulator outperforms execution on Xeon 2.80 GHz by approximately 80 times, even with large-scale biochemical systems

A reconfigurable biochemical simulator by solving ordinary differential equations has received attention as a personal high speed environment for biochemical researchers. For efficient use of the reconfigurable hardware, static scheduling of high-throughput arithmetic pipeline structures is essential. This paper shows and compares some scheduling alternatives, and analyzes the tradeoffs between performance and hardware amount. Through the evaluation, it is shown that the sharing first scheduling reduces the hardware cost by 33.8% in average, with the up to 11.5% throughput degradation. Effects of sharing of rate law functions are also analyzed.

Today, mathematical modeling and simulation of biochemical pathways take a major role in biological researches. However, modern microprocessors cannot provide enough throughputs to explore the large parameter space of target pathways. To address this problem, ReCSiP (a reconfigurable cell simulation platform), an FPGA-based biochemical simulator is proposed. It's an ODE-based simulator, which solves the rate-law functions. The framework proposed in this paper, enables to simulate pathways consisting many different types of chemical reactions by connecting the rate-law modules (solvers) on an FPGA. It provides the solver-to-solver communication mechanism on an FPGA and automatic configuration software to generate the circuit.