In this brief contribution a new algorithm-based concurrent error detection scheme employing the checksum approach is proposed for FFT networks. Our design allows high error coverage with low false alarm rate by applying the linear weight factors to the checksums. Due to the simplicity, the hardware overhead is relatively small and errors can be quickly detected. The design is also shown to be easily expanded for multidimensional FFT networks.>

Currently large digital systems consist of a control unit and many processing units. Much work has been done in partitioning large processing units (PUs) into multiple PUs. However, there is still a large control unit that must control each of these PUs. This results in long lines from the control unit to the PUs and hence a long clock period. We present a method to break the control unit into many smaller control units (local CUs) so that each of these local CUs can sit on the same chip as the PU that it controls. These local CUs are partitioned in such a fashion that there is a pipelined sequence of execution between them.>

A methodology for the register allocation problem in high-level synthesis based on the scanline sweep algorithm is introduced. The algorithm is computationally efficient and easy to understand and to implement, and it guarantees an optimal number of registers for nonpipelined designs. In this method, a set of registers is available from which the best one can be chosen by the allocator for variable binding. The method has proved to be useful in constructive allocation strategies in which the operators and variables are simultaneously considered for binding for interconnect cost optimization. The allocation program is written in C and it is integrated into the DAGAR high-level synthesis system.>

An automated microarchitecture synthesis system called DAGAR is presented. DAGAR takes as input a behavioral description of a digital system and outputs a microinstruction (MI) sequence and a data path. In microarchitectures synthesized by DAGAR the functional units (FUs) may take one or more clocks (i.e. MIs) to perform an operation. These are called multiclocked FUs. Additionally, if these FUs can accept new data while processing data from a previous MI, they are called pipelined FUs. The use of pipelined FUs is shown to decrease the number of FUs in the data path without a time penalty. Unlike other systems, DAGAR deals with the partitioning of a single FU into stages.>