In the rapidly evolving landscape of System-on-Chip (SoC) design, Intel has faced unique Design-for-Testability (DFT) challenges that commercially available Electronic Design Automation (EDA) solutions could not address. This paper explores Intel’s transition from a proprietary hybrid test and debug integration solution to a new, innovative DFT integration solution based on industry standards and Siemens’ Tessent Platform. The new solution integrates both proprietary and vendor-provided DFT logic, addressing the shortcomings of the legacy flow. This paper details the challenges of the legacy solution, the development of the new solution, and its impact on future SoC design and testing at Intel.

Functional state extraction of both sequential logic and arrays in a design is widely used in the industry to debug logic and timing bugs. Typically, this is done by repurposing logic and array test DFT that is already present in the design. In this paper, we describe the logic state extraction methodology as practiced in Intel servers, which is referred to as "scan dump". First, we motivate the state extraction problem and provide contextual background. Secondly, we describe design-for-test (DFT) implementation in support of scan dump for state extraction. Thirdly, we describe the pre-silicon validaion methodology for scan dump. Fourthly, we describe a set of best practices for implementing the scan dump feature. Finally, we describe an actual debug example using scan dump.

Stress test is a common practice in the industry for accelerating latent defects and to pull in early life failures. Stress test requires voltage and temperature elevation for screening latent defects. This in turn implies that static timing analysis (STA) needs to be done at elevated voltage and temperature conditions. Timing closure at elevated voltages increases design area, power dissipation, and timing convergence effort. We present a relaxed timing closure methodology that targets timing closure in select DFT logic. Secondly, to ensure that the required switching activity needed for stress is achieved in the design, a specialized toggle monitor circuit is introduced. The toggle monitor can check for sign-of-life during stress test. Use of toggle monitor and relaxed timing closure on select DFT logic mitigates the design impact of timing closure at elevated voltages. Finally, it is observed on silicon that the stress content is applied correctly.

System-on-Chip (SoC) designs are increasingly difficult to test using traditional scan access methods without incurring inefficient test time, high planning effort, and physical design/timing closure challenges. The number of cores keeps growing while chip pin counts available for scan remain constant or decline, limiting the ability to drive cores concurrently. With increasingly commonplace tiling and abutment, the scan distribution hardware must be placed inside the cores, making balanced pipelining when broadcasting to identical cores difficult. optimizing test time requires analyzing all the cores and subsequently changing the test hardware in the cores. Internal shift speed constraints may limit the ability to shift data in and out of the chip at high rates. Differences in pattern counts or scan chain lengths between cores tested in parallel can result in padding and increased test time. SSN is a bus-based scan data distribution architecture designed to address all these challenges. It enables simultaneous testing of any number of cores even with few chip I/Os. It facilitates short test time by enabling high-speed data distribution, by efficiently handling imbalances between cores, and by supporting testing of any number of identical cores with a constant cost. It provides a plug-and-play interface in each core that is well suited for abutted tiles, and simplifies scan timing closure. This paper also compares the test cost and implementation productivity of SSN with those of Intel's Structural Test Fabric.

This paper presents new fault models, test algorithms and simple DFT for testing a class of likely faults in multi-ported, word-organized register files.

Comprehensive transition scan content was deployed on an Intel®Itanium®server microprocessor design, including full coverage patterns for all core logic blocks. Since this was the first time at-speed scan patterns were being planned as a manufacturing screen on an Intel®CPU core design, the test deployment team needed to ensure that all concerns of over-and under-testing were systematically addressed. A few innovative and novel DFT solutions were deployed to ensure that the post-silicon team had the adequate tools to fully analyze the at-speed scan content. This paper describes these DFT solutions that proved invaluable during this process.

Lessons learnt during the deployment of transition scan content on an Intel®Itanium®server microprocessor design and its use for electrical debug and defect screening in high-volume manufacturing are described. While many publications in the area of transition scan show it being practiced as an efficient defect screening tool, only a minority of these designs were high-performance microprocessor designs. This work illustrates the benefits of such techniques on complex microprocessors.

Voltage transients from circuit activity impact operation, testing and debug of complex designs. This paper describes a system which enables voltage transient detection and a capability to induce voltage transients in a controlled manner. Usage models and silicon results are described, along with limitations and future options for improvements.

The paper explores the effects of power-supply droop during scan based at-speed test application. The unnatural supply voltage profile that results when the capture clocks are fired during such tests can lead to artificial failures and bring into question the validity of using structural at-speed testing as a delay defect screen. The experiments described in this paper attempt to fully characterize this effect in a number of different ways. Although the focus of this publication is mainly transition scan patterns, the results are equally applicable to path-delay scan testing.

Switching activity-generated power-supply grid-noise presents a major obstacle to the reduction of supply voltage in future generation semiconductor technologies. A popular technique to counter this issue involves the usage of decoupling capacitors. This paper presents a novel design technique for sizing and placing on-chip decoupling capacitors based on activity signatures from the microarchitecture. Simulation of a typical processor workload (SPEC95) provides a realistic stimulation of microarchitecture elements that is coupled with a spatial power grid model. Evaluation of the proposed technique on typical microprocessor implementations (the Alpha 21264 and the Pentium II) indicates that this technique can produce up to a 30% improvement in maximum noise levels over a uniform decoupling capacitor placement strategy.

A new methodology involving effect-cause analysis has been demonstrated for the diagnosis of path delay faults. The paper illustrates a structural representation, called the suspect circuit, of all the possible path delay faults in a faulty circuit. This representation has been used to design efficient algorithms that enable us to manipulate the suspect faults without having to enumerate them explicitly. Procedures for removing fault-free paths from the list of suspect faults have been implemented to improve the diagnostic resolution. Moreover, efficient data structures are used to complement the procedures and reduce the memory footprint of the algorithms. Results indicate that the diagnostic resolution obtained is very high and includes all possible causes of the observed delay faults.

A new methodology is developed in this paper for identifying possible path delay faults through at-speed testing of sequential non-scan circuits. In the past, different techniques have been proposed for diagnosing delay faults in sequential circuits through variable clock control techniques. These techniques are, however not readily applicable to commercial high-performance ICs. We propose new techniques based on critical-path tracing which can be used to locate slow paths in sequential circuits. Strategies have been developed to improve the diagnostic resolution, which involve deducing internal state values from the observed circuit outputs and the detection of fault-free circuit paths. Results of experiments on the ISCAS89 sequential benchmark suite are finally discussed.

A novel methodology involving effect-cause analysis has been demonstrated for the diagnosis of path delay faults. We seek to provide an improved understanding of the methods introduced by Y.-C. Hsu and S.K. Gupta (1998), with the goal of devising efficient representations and algorithms for the diagnosis of path delay faults. Results indicate that the diagnostic resolution obtained is very high and includes all possible causes of the observed delay faults.

Article An architectural solution for the inductive noise problem due to clock-gating Share on Authors: Mondira Deb Pant Georgia Institute of Technology, Atlanta, GA Georgia Institute of Technology, Atlanta, GAView Profile , Pankaj Pant View Profile , D. Scott Wills Georgia Institute of Technology, Atlanta, GA Georgia Institute of Technology, Atlanta, GAView Profile , Vivek Tiwari Intel Corporation, Santa Clara, CA Intel Corporation, Santa Clara, CAView Profile Authors Info & Claims ISLPED '99: Proceedings of the 1999 international symposium on Low power electronics and designAugust 1999 Pages 255–257https://doi.org/10.1145/313817.313938Online:17 August 1999Publication History 42citation309DownloadsMetricsTotal Citations42Total Downloads309Last 12 Months0Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

We demonstrate a new approach minimizing the total ofthe static and the dynamic power dissipation components in aCMOS logic network required to operate at a specified clockfrequency using joint optimization of both device and circuitdesigns for a specific logic schematic and activity profile.We present a new approach to designing ultra low-powerCMOS logic circuits by joint optimization of supply voltage,threshold voltage and device widths for a specified speedconstraints.The static (leakage) and dynamic (switching)energy components are considered and an efficient heuristicis developed that delivers over an order of magnitude savingsin power over conventional optimization methods.

In this paper we propose to use an output signal waveform analysis method called signal waveform integration for detection of stuck-at failures in combinational circuits. Non-robust tests are applied at-speed or faster to achieve high fault coverage, low test application time and detectability of redundant faults using directed random test generation techniques.