As the Internet of Things (IoT) technology matures and becomes widely adopted, security for IoT networks remains the main concern for users and organizations across the globe. The full potential of IoT technology will not be realized without a robust security solution. IoT sensors are considered weak links in IoT networks that can be utilized to access key information or to attack IoT networks. In this work, a new technique is presented to detect hardware Trojans. It is shown how to amplify the side-channel leakage of a Trojan to increase its observability and the detection rate. In the proposed solution, the effect of adding a Trojan on the supply path is observed to detect the Trojan. Experimental measurement results on a prototype demonstrate that the proposed method can increase the observability for a Trojan by more than tenfold without increasing the signal-to-noise ratio. Small size Trojans, which remain undetected using conventional methods, can be identified with the proposed solution.

Design for Testability (DfT) techniques allow devices to be tested at various levels of the manufacturing process. Scan architecture is a dominantly used DfT technique, which supports a high level of fault coverage, observability and controllability. However, scan architecture can be used by hardware attackers to gain critical information stored within the device. The security threats due to an unrestricted access provided by scan architecture has to be addressed to ensure hardware security. In this work, a solution based on the Clock and Data Recovery (CDR) method has been presented to authenticate users and limit the access to the scan architecture to authorized users. As compared to the available solution the proposed method presents a robust performance and reduces the area overhead by more than 10%.

Physical defects in capacitive MEMS devices can change the nominal device capacitance by a few femtofarads. Detecting such small variations is challenging particularly in the presence of Process, Temperature, and supply Voltage (PVT) variations. A test solution utilizing a phase locking circuit is presented in this paper to minimize the effect of PVT variations on fault detection. A Delay Locked Loop (DLL) is modified to amplify small capacitance variation in order to detect structural faults of capacitive MEMS devices in the time domain. The measurement results on a prototype using 0.18-μm CMOS indicate that a physical defect changing the nominal capacitance of the device-under-test by 2 fF can be detected using the proposed method.

Security is the main challenge in the design and implementation of today's ubiquitous interconnected objects on the Internet network infrastructure. Many security solutions have been already proposed to address security concerns for IoT enabled devices. In this paper, an integrated approach for authentication and access control is presented for communication with wireless sensor nodes in IoT networks. The proposed method provides strong protection against known attacks such as energy exhausting, and Man-In-The-Middle.

This paper presents a fine-coarse time interval measurement scheme which is resilient to the variations of process, voltage, and temperature (PVT). Two Delay Locked Loops (DLLs) have been utilized to minimize the effects of PVT on the measured time intervals. A two-step time-to-digital converter is designed to ensure a high-resolution measurement over a wide dynamic range. The proposed scheme has been implemented using CMOS 65nm technology. Simulation results using ADS tools indicate that the measurement resolution varies by less than 0.12ps with ±15% variations of power supply voltage. The proposed method also presents a robust performance against process and temperature variations. The measurement resolution changes by few femto-seconds from slow to fast corners for process variations and it varies by a maximum of 0.1ps with changes from −40 °C to +100 °C in temperature.

There is a tradeoff between the requirements for security and testability for a sensor node hardware. To test a sensor, it is desired to have access to the internal circuitry of the Device-Under-Test (DUT) to apply test stimuli and observe its responses. While such unrestricted access to the DUT is desired for testing, it can undermine the security. To secure a sensor node from attacks by malicious attackers, it is imperative to limit user access once the device has been adopted for in-field use. Efficient design-for-testability (DFT) techniques have been developed without taking into consideration the security threats posed by them. For instance, scan structure which is widely deployed in modern digital circuits, can be used as an effective tool to wage an attack and extract critical information from cryptographic cores. In this work, a new solution is presented to protect sensor nodes containing crypto-cores against scan-based attacks without compromising their testability at the manufacturing phase. In the proposed solution, a built-in self-test (BIST) technique is developed to carry out in-field tests for crypto-cores while a scan-based test method is utilized for manufacturing test. The proposed method prevents scan-based attacks without compromising testability during the manufacturing phase.

The concept of indoor location positioning has been around for decades now. Despite the existence of many algorithms that can achieve location positioning with remarkable performance in terms of accuracy, implementation of such algorithms has not been done on a large scale. There is a trade-off between the positioning accuracy and the complexity of the algorithm. This paper introduces and explains a method that is lightweight in terms of complexity and cost which can be used to perform indoor location positioning. The proposed algorithm does not require a radiomap or a server, which makes it suitable for systems with limited processing power such as mobile nodes, drones, and small autonomous intelligent machines.

Scan based Design for Test (DfT) schemes have been in wide use to increase the testability of digital circuits. The main objective is to ensure that nodes in the Circuit Under Test (CUT) are controllable and observable. While such comprehensive access is highly desirable for testing, it is not acceptable for secure chips as it is subject to exploitation. In this work, a new method is presented to protect the sensitive information from attackers using scan chains. The access through the scan chain to the circuit containing the secret information has been severely limited to reduce the risk of a scan-based attack. To ensure the testability of the circuit, a built-in self-test utilizing an LFSR is considered. The proposed scheme can be used as countermeasure against side channel attacks with a low area overhead as compared to the reported solutions.

This paper presents a new chipless radio-frequency identification (RFID) tag using microelectromechanical systems (MEMS) technology. The tag can operate at the conventional UHF band for RFID applications and can be implemented using a basic fabrication process. In the presented scheme, MEMS switches are used as programmable elements to support communication between the tag and RFID interrogators. Experimental measurements on a fabricated prototype indicate that the implemented tag can successfully communicate with an RFID reader. The measured S-parameters of the tag show less than 1 dB insertion loss and -17 dB return loss at 910 MHz center frequency.

Through silicon via (TSV) is the enabling technology for 3-D integrated circuit (IC) realization. To develop manufacturing tests for 3-D ICs, TSV has to be accurately modeled. Analytical methods are commonly used to develop circuit models for TSVs. These models are often difficult to develop and require some assumptions to simplify the problem. This paper presents a new method utilizing computer-aided design tools to extract circuit models for prebond and postbond TSVs. It is shown how the effects of common TSV parametric and catastrophic faults such as pinholes, voids, and open circuits affect TSV circuit models through 3-D full-wave simulations. It is also shown that the substrate conductivity has a considerable effect on the TSV fault characterization. The extracted models indicate that even a relatively large void does not alter the TSV characteristic parameters and thus voids remain largely undetected with conventional test solutions. An on-chip circuit, utilizing a delay-locked loop is presented as a test solution to detect TSV parametric faults.

Location positioning in indoor environments is a major challenge. Various algorithms have been developed over years to address the problem of indoor positioning. One of the most cost effective choice for indoor positioning is based on received signal strength indicator (RSSI) using existing Wi-Fi networks in commercial and/or public areas. This solution is infrastructure-free and offers meter-range accuracy. In this paper, machine learning approaches including k-nearest neighbor (k-NN), a rules-based classifier (JRip), and random forest have been investigated to estimate the indoor location of a user or an object using RSSI based fingerprinting method. Experimental measurements were carried out using 1500 reference points with received RSSIs of 86 installed APs in the second floor of Centre for Engineering Innovation (CEI) building at the University of Windsor. The results indicate that the random forest classifier presents the best performance as compared to k-NN and JRip classifiers with positioning accuracy higher than 91%.

In low-power VLSI design good amount of power can be saved by using coding scheme such as Bus-Invert (BI). Such a coding scheme looks at successive words on a data bus and applies transformation to minimize the number of transitions. In this paper we propose Bus-Shift (BS) coding scheme that circularly shifts the data to minimize transitions. Power saving of BI is poor on average cases, and even that deteriorates with wider bus width. In comparison the proposed BS scheme performs better in both maximum and average cases. For wide bus the savings from BS gets slightly worse, but still performs better than BI. Simulation results show a saving margin of 14% in average cases for a 32 bit bus. Comparison is also made with Shift-Invert (SINV), another reported coding scheme. An implementation of BS in Cadence is presented.

In this paper a test method for MEMS devices is presented in which physical defects are detected in the frequency domain rather than the time domain. A resonator, that can be part of a read out circuit, is utilized to test capacitive Micro-Electro-Mechanical Systems (MEMS). The proposed technique is based on the principle of resonant frequency where variations of the resonant frequency are observed to detect structural defects. To verify the validity of the proposed approach, a MEMS comb-drive is designed and fabricated. Measurement and simulation results indicate that the proposed method can be used to capture common comb-drive defects such as missing or broken fingers, shorted fingers and tilted arms.

Silicon interposer is the enabling technology for 2.5D IC integration which supports higher levels of integration and improved electrical performance. An interposer can suffer from various physical defects affecting the overall performance of 2.5D ICs. This paper presents a new method to perform manufacturing tests for interposers utilizing a Delay Locked Loop (DLL). In the proposed method short-time intervals are first amplified through a time-amplifier and then measured. Simulation results using ADS software with 65 nm TSMC CMOS technology indicates that proposed method can detect minor structural defects affecting the propagation delay of interconnect by more than 1.5ps resolution.

This study presents a new test method for Through Silicon Via (TSV) in 3D stacked ICs, in which a Delay-Locked Loop (DLL) is utilized to detect TSV defects. As compared to TSV test methods using free running ring oscillators, the proposed method presents a much better performance against Process, supply Voltage and Temperature (PVT) variations due to the inherent feedback of DLL systems. In the proposed scheme, a periodic signal is applied to the TSV under test and the propagation delay is measured to detect TSV faults. To perform circuit level simulations, 3D full-wave simulations are performed to extract accurate spice models for both faulty and fault free TSVs. Simulation results indicate that the proposed test solution can detect TSV manufacturing defects, changing its propagation delay by more than 10% from the nominal value.

A contactless TSV probe based on the principle of resonant inductive coupling is presented in this work. The proposed scheme allows TSV data observation up to 2Gbps when the probe and TSV are 15μm apart.

In this paper, three coupling techniques for contactless TSV probing have been presented and their advantages and disadvantages are discussed. A contactless, noninvasive TSV probing scheme based on the principle of capacitive coupling is designed and simulated. The implemented scheme supports the high-density and the tight-pitch requirements for TSV probing.

In this paper, we present a new readout circuit with an integrated built-in self-test (BIST) structure for capacitive microelectromechanical system (MEMS). In the proposed solution, instead of commonly used voltage control signals to test the device, charge-controlled stimuli are employed to cover a wider range of structural defects. The proposed test solution eliminates the risk of structural collapse in the test phase for gap-varying parallel-plate MEMS devices. Measurement results using a prototype fabricated in TSMC 65-nm CMOS technology indicate that the proposed BIST scheme can successfully detect minor structural defects altering MEMS nominal capacitance.

Testing the integrity of interconnects realized by through silicon vias (TSVs) in 3-D integrated circuits (3-D IC) is considered a challenging task. TSVs are excessively small and fragile for current probe technology. In this paper, a new spring-type probe using microelectromechanical systems (MEMS) technology is presented. The implemented MEMS probe supports the required pitch for TSV direct probing and minimizes the undesired scrub marks on TSV surface. Simulation results indicate that the implemented MEMS probe can operate at the gigahertz frequency range without significant test signal degradation.

A new Built-in Self-Test (BIST) method for capacitive Micro-Electrical-Mechanical System (MEMS) devices using charge-control method has been developed in which the Device Under Test (DUT) is stimulated through current sources. The DUT output signals are first converted to time domain intervals and then measured through a precision Time-to-Digital converter (TDC). The proposed BIST scheme supports self-calibration and produces robust results under process, supply and temperature variations. Simulation results indicate that this method can successfully detect minor structural defects altering the MEMS nominal capacitance by 70af.

The trade-off between pedestal error and acquisition time limits the level of speed-accuracy that can be achieved by CMOS track-and-hold circuits. This paper presents a circuit technique to design a high-resolution, high-speed T/H circuit. The sampling error produced by clock feedthrough and the charge injection of CMOS switches are eliminated through a cancellation technique using a replica circuit. Simulation results using CMOS 90 nm process confirm that the proposed method lowers the pedestal error considerably and supports linearity over 9.8 effective bits at 500 MHz sampling rate for input signals up to 10 MHz.

At gigahertz frequency range, performance degradation of the device interface board increases the yield loss and the cost of manufacturing. In this poster a MEMS based solution is proposed to design a Device Interface Board (DIB) supporting high-speed connectivity between the device under test and the tester. Simulation results indicate that the proposed scheme can operate up to 50 GHz without considerable signal integrity degradation.

This paper describes the test and measurement of high-frequency analog/RF cores in a mixed-signal system-on-chip (SoC) environment using an embedded tester core. A new test methodology has been developed in which high-frequency tests are performed on-chip, but the control and test results are transmitted over the lower bandwidth connectivity associated with the SoC I/O terminals. A low-frequency analog signal is used to modulate a high-frequency squarewave and the resulting waveform is applied to a high-frequency circuit-under-test (CUT) as a test stimulus. The CUT's response is sampled using a coherent subsampling technique and the captured samples are transmitted at low-speeds off-chip from the SoC. A coupled phase-locked-loop and delay- locked-loop structure is employed to generate test waveforms in the 2.7-GHz range and to support high-resolution sampling with a sampling resolution of less than 10 ps. Simulation results using a reference low noise amplifier as a CUT shows the effectiveness of the proposed test method. The tester core has been sent for fabrication in CMOS 0.18-mum technology with a target area of 1 mm2.