Predicting the Single-Event Effects in integrated circuits before their fabrication and ultimately estimating their cross-section would be of much interest to the space industry. For high-performance analog and mixed-signal circuits, radiation-hardening design flows routinely include Single-Event electrical simulation to identify the most sensitive nodes. If we can identify the sensitive area of the circuit to the PN-diodes connected to the sensitive nodes, we should thus be able to get an estimate of the cross-section. In this work, we show that this is far from being reality by comparing the results of electrical simulations to the cross-sections obtained by radiating a rad-hard reference generator for a high-performance ADC with Heavy Ions. A deep analysis of the results suggests that there are unmodelled effects at stake that dominate the experimental cross-section.

One of the most critical radiation effects, because it is potentially destructive, is the Single-Event Latchup (SEL). Positive feedback in parasitic bipolar structures, triggered by a current pulse induced by an ionizing particle, creates a low impedance path between supply and ground. If the supply is not rapidly shut down, high currents can cause burnout or metal opens. Any radiation campaign must thus implement some protection at the board level to properly detect the onset of a latchup and shut the circuit power down. This paper describes an SEL detection platform, designed for a 13b 40Msps ADC prototype, that takes into account the specific requirements of high-precision Analog and Mixed-Signal circuits.

This article proposes a behavioral model, based on closed-form equations, of the dynamic errors in high-speed high-accuracy successive approximation register (SAR) analog-to-digital converters (ADCs) with charge-redistribution capacitor-based digital-to-analog converters (CDACs). To deal with incomplete settling of references and overcoming$LC$package parasitics, on-chip generation of the references must be considered in high-performance applications. This architecture, in combination with a bit-redundant conversion scheme, improves conversion speed while relaxing power consumption. The main challenge in this approach is that the reference settling and the resulting redundancy tolerance are signal-dependent, not only on the current error magnitude but also on the previous conversion cycle history and parasitics. This requires costly postlayout transistor-level simulations for performance evaluation (in the order of days), making not always feasible a systematic exploration of design space before integration due to computation time. To overcome this bottleneck, this work will show that the dynamic behavior can be theoretically predicted using a time-varying effective reference, the behavior of which is analytically described compactly. The accuracy of the proposed dynamic model is verified with a comparison with a 1.2-V 13-bit 65-nm SAR ADC characterized between 10 and 60 Msps at the postlayout level.

This paper presents an innovative integrated load-pull bench at 160 GHz. The proposed system, which is designed in a 55-nm BiCMOS technology, is tailored to deal with all of the measurement functions including signal generation, shaping, and magnitude and phase measurement. This system will allow precise characterization of Devices-Under-Test (DUTs) (i.e., circuits and/or devices) when integrated together with the DUT. In addition, the proposed system could also be envisioned as a System-on-Chip (SoC) that, when reported into an RF probe, could serve as a test bench for any integrated circuit.

This paper presents a novel Look-up Table (LUT) calibration technique for static non-linearity compensation in analog-to-digital converters (ADCs) with digital redundancy, such as Successive Approximation Register (SAR), Algorithmic, Sub-ranging or Pipeline ADCs. The method compensates the performance limitations of the conventional LUT approach in presence of comparison noise and/or non-monotonicity. In these circumstances, the input-output transfer function of a redundant ADC becomes significantly multivalued - that is, different output codes can be achieved for the same input level at different time instants. This behavior is motivated because from sample to sample, in a design with redundancy, the processing signal path is not unique, causing that the error under calibration becomes time-dependent, something which is not contemplated in the conventional calibration model. To deal with this effect, this work proposes a digital low-cost post-processing of the standardized Integral-Non-linearity (INL), which resolves multivalued situations using a direct access to the internal redundant codes. The method improvements are validated by realistic SAR and Pipeline ADC case studies at behavioral level, and by experimental data from an 11-bit 60Msps Pipeline ADC implemented in a 130nm CMOS process. These experimental results show that the proposed calibration achieves an improvement of approximately 1.6 effective bits at full-scale input amplitude.

The test of analog, mixed-signal and RF (AMS-RF) circuits is still considered as a matter of human creativity, and although many attempts have been made towards their automation, no accepted and complete solution is yet available. Indeed, capturing the design knowledge of an experienced analog designer is one of the key challenges faced by the Electronic Design Automation (EDA) community. In this paper we explore the use of causal inference tools in the context of AMS-RF design and test with the goal of defining a methodology for uncovering the root causes of performance variation in these systems. We believe that such an analysis can be a promising first step for future EDA algorithms for AMS-RF systems.

Integrated millimeter-wave (mm-wave) circuits fabricated in current nanometric processes are especially sensitive to process variations. This issue produces shifts in the circuit performance that may significantly reduce the fabrication yield. In this line, per-die characterization and trimming are usually required for mm-wave integrated circuits, but this is an expensive and time-consuming task to be performed at the production line. Embedded calibration for mm-wave circuits is an appealing alternative to enhance yield that may overcome some of these issues. In this work we present a two-stage 60 GHz power amplifier (PA), designed in STMicroelectronics 55 nm CMOS technology, that features a one-shot calibration procedure for process variation compensation based on non-intrusive process monitors. We present the design of a tuning knob based on variable decoupling cells which have been implemented within the PA for calibration purposes. The proposed one-shot calibration procedure reads the output of the embedded process monitors and then relies on a machine learning regression model to find the best configuration of the tuning knobs for optimizing the performance of the circuit and enhance fabrication yield.

In safety critical applications there is a demand for estimating defect coverage in order to meet stringent quality levels. However, defect simulation of complex AMS-RF circuits is computationally expensive since achieving good confidence interval requires sampling many defects. In this paper, we show on a practical case of study that it may be beneficial to complement defect coverage with fault coverage and assess the severity of defect escapes to get a complete picture of test quality.

Testing analog, mixed-signal and RF (AMS-RF) circuits represents a significant cost component for testing complex SoCs. Moreover, AMS-RF test generation and validation are still largely handcrafted tasks that rely on expert design knowledge for each particular Device Under Test (DUT). Mixed-signal test automation has been sought by the test community for the last decades, trying to mimic the success of digital test approaches. Indeed, in the digital domain, test is vastly automated and standard techniques are already available (ATPGs, BIST, scan registers, etc.). In the last decade, a methodology based on leveraging the power of machine learning algorithms has been proposed for AMS-RF circuits that opens the door to a higher level of automation. In this paper we review recent results in this line and try to put together what could be such a complete methodology and what remains to be done.

Testing analog, mixed-signal and RF circuits represents the main cost component for testing complex SoCs. A promising solution to alleviate this cost is the machine learning-based test strategy. These test techniques are an indirect test approach that replaces costly specification measurements by simpler signatures. Machine learning algorithms are used to map these signatures to the performance parameters. Although this approach has a number of undoubtable advantages, it also opens new issues that have to be addressed before it can be widely adopted by the industry. In this paper we present a machine learning-based test for a complex mixed-signal system - i.e. a state-of-the-art pipeline ADC-that includes digital calibration. This paper shows how the introduction of digital calibration for the ADC has a serious impact in the proposed test as calibration completely decorrelates signatures from the target specification in the presence of local mismatch.

This paper presents a self-testable BIST application for non-linearity test in high-speed high-performance ADCs in nanometric CMOS technologies. The technique makes use of an on-chip low-frequency signal generator optimized toward high accuracy, followed by a dedicated buffer based on a resistive feedback amplifier. This buffer has two main features: it isolates the on-chip generator output from the high-frequency switching noise at the input sampling of the ADC under test, and it allows a robust injection of a controlled offset to apply double-histogram techniques for linearity evaluation. This approach results in a true self-testable BIST strategy making feasible the simultaneous estimation of the non-linearity for both the generator and the ADCUT. In order to verify the feasibility and performance of the proposed circuitry, a practical design in a 1.8V 0.18μm CMOS process is presented here as demonstrator. Transistor-level simulation results with a 2Vpp sinusoidal test-stimulus show an effective resolution in static conditions greater than 15 bits, being a suitable solution for the ADC static test with effective resolutions in the order of 13 bits and 100Msps of sampling frequency.

Machine learning indirect test - also known as Alternate Test- has shown its potential to reduce test cost while maintaining an interpretation of the results compatible with the standard specification-based test. Since its introduction, many papers have been proposed to refine the idea and address its shortcomings. In particular, the issue of early validation of the test at the design stage has been considered and some methodologies have been proposed to assess test quality. These methodologies rely essentially on Monte Carlo simulations. In this paper, we propose a set of thought experiments to show that small inaccuracies and variations in the Monte Carlo models included in current technology process design kits may have a significant impact in the validation of machine learning indirect test, in particular in the estimation of test quality metrics. Despite of this, machine learning indirect test has actually succeeded in actual industrial cases. Some hints are thus given to the conditions that the test has to fulfill to guarantee good results.

Alternate Test has demonstrated in the last decade that advanced machine-learning tools can leverage the accuracy gap between functional test and indirect, or model-based, test. If a regression approach is taken, a model should be trained for each specification. The advantage is that the results are interpreted just like performance measurements but the drawback is that accuracy is required over the full variation range. On the other hand, a classification approach can be seen as a wiser solution since it locates the pass/fail boundary, which inherently contains all the specification information, in the cheap measurement space. Cost optimization due to imbalance between test escape and yield loss is usually handled by guard-banding on specifications. This is straightforward to translate to regression-based Alternate Test but not for classification-based. This paper shows that two different asymmetric approaches consistently outperforms an off-the-shelf symmetric algorithm. The first technique is based on manipulating the decision threshold while the second technique directly builds an optimized pass-fail boundary by considering different costs to penalize test escapes and yield losses.

The process of testing Integrated Circuits involves a huge amount of data: electrical circuit measurements, information from wafer process monitors, spatial location of the dies, wafer lot numbers, etc. In addition, the relationships between faults, process variations and circuit performance are likely to be very complex and non-linear. Test (and its extension to diagnosis) should be considered as a challenging highly dimensional multivariate problem.

Pipeline Analog to Digital Converters (ADCs) are widely used in applications that require medium to high resolution at high acquisition speed. Despite of their quite simple working principles, they usually form rather complex mixed-signal blocks, particularly if digital correction and calibration are considered. As a result, pipeline converters are difficult to test and diagnose. In this paper, we propose to reconfigure the internal Multiplying DACs (MDACs) that perform residue amplifications as integrators, each one with an analog and a digital input. In this way, we can reuse consecutive pipeline stages to form ΣΔ modulators, with very reduced area overhead. We thus get an on-chip DC (low-frequency) probe with a digital 1-bit output that does not require any extra pin. In addition, digital test techniques developed for ΣΔ modulators may be used to enhance the diagnosing capabilities. An industrial 1.8V 15-bit 100Msps pipeline ADC that had previously been fully validated in a 0.18μm CMOS process is used as a case of study for the introduction of the DfT modifications.

This work proposes a generic methodology for selecting meaningful subsets of indirect measurements (signatures). This allows precise predictions of the DUT performances and/or precise pass/fail classification of the DUT, while minimizing the number of necessary measurements. Two simple figures of merit are provided for ranking sets of signatures a priori, before training any machine learning model. These two figures evaluate the quality of each signature based on its Brownian distance correlation to the target specifications, and on its local distribution in the proximities of the pass/fail decision boundaries. The proposed methodology is illustrated by its direct application to a DC-based alternate test for LNAs.

This work presents a modification of traditional Oscillation-Based Test schemes for sampled-data systems. This new test scheme is based on doubling the sampling frequency when the oscillation changes its sign. This way, the DC level of the output oscillation signal becomes a simple signature sensitive to the settling errors in the device under test and to its oscillation features. The proposed technique is illustrated on a switched-capacitor second-order lowpass filter. This case study is used to show the sensitivity of the proposed signature to the linearity of the DUT. Electrical simulation results are provided to validate the proposal.

This work demonstrates that multi-VDDconditions may be used to improve the accuracy of machine learning models, significantly decreasing the prediction error. The proposed technique has been successfully applied to a previous alternate test strategy for LNAs based on response envelope detection. A prototype has been developed to show its feasibility. The prototype consists of a low-power 2.4GHz LNA and a simple envelope detector, integrated in a 90 nm CMOS technology. Post-layout simulation results are provided to verify the functionality of the approach.

This work presents a SigmaDelta modulator prototype that gives experimental support to a fully digital built-in self-test scheme. The goal of the proposed BIST is to provide digital signatures that are directly related to some important behavioural parameters of SigmaDelta modulators. As a result, parametric drifts can be detected before they seriously affect performance. The modulator required modifications are minimal and few gates would be necessary to implement a full BIST version, enabling infield self-test

This paper presents a digital structural test for first-order Sigma-Delta modulators. A periodic digital sequence is used as a stimulus to obtain a signature of the integrator leakage. This parameter is known to be related to the modulator precision and its estimation is of great importance to assess if the modulator works as expected. As the proposed technique is fully digital, it is especially suitable to test modulators embedded in complex mixed-signal circuits.

This paper presents practical solutions for two of the main topics arising when applying oscillation-based-test: the start-up of the configured oscillator and the on-chip evaluation of the generated test signals. The required circuitry is very simple and robust. Moreover, preliminary results obtained from an integrated prototype are also included.