This study evaluates the usability of Alfaba, a multi-sensory educational tool specifically designed to support literacy development for children and young people with Down Syndrome (DS). Alfaba integrates tactile, visual, and auditory feedback, aiming to facilitate letter recognition, phoneme association, and word construction in a manner aligned with the cognitive and motor needs of this population. A usability test was conducted with seven participants aged 7 to 17, focusing on their interactions with Alfaba to assess accessibility, engagement, and areas for improvement. The results highlight that Alfaba's tangible design and real-time feedback encourage independent learning, support error recognition, and foster motor skill development, making it a valuable literacy tool for individuals with DS. Additionally, the study identifies opportunities for enhancement, such as incorporating touchscreen capabilities, gamified elements, and customizable word groups to further engage users. Alfaba's adaptability to the Brazilian Portuguese phonetic structure also positions it as a culturally inclusive tool that addresses the specific phonological needs of Portuguese-speaking children with DS. This study contributes to the field of inclusive educational technology by offering design recommendations that can enhance Alfaba's impact on literacy and proposes directions for future research to further refine and assess its efficacy in controlled educational settings.

Alfaba, presented in this paper, is a low-cost, multi-sensory educational tool tailored to enhance literacy in underprivileged children. It leverages neuroplasticity principles, employing a tactile, interactive approach to develop essential neural connections for reading and writing. Tested with 11 children aged 7 to 10 years, its usability evaluation demonstrated effectiveness and user-friendliness, particularly in socially vulnerable contexts. Its cost-effectiveness makes Alfaba accessible in resource-limited settings, aiming to reduce educational disparities. Alfaba's innovative design focuses on providing equal learning opportunities for all children, regardless of socioeconomic background, making it a significant step toward educational equity and demonstrating the inclusive integration of technology in education for widespread impact.

The Covid-19 pandemic has driven students out of schools around the world. In Brazil, a developing country, this dropout has damaged the literacy of students between the ages of 5 and 9. We are running against the clock, and solutions to develop skills to promote reading and writing are fundamental. For students with learning difficulties, the damage is even greater. Dyslexic students have difficulties that naturally make this step even more complex for them. This work presents Alfaba: a tangible solution developed with low-cost hardware that stimulates literacy skills. Alfaba got evaluated by professionals and teachers and prototyped to support not just dyslexic students, but every student that needs to be supported at this stage of their learning journey. Our results show that Alfaba meets the needs of students and that its functions are consistent with the skills to be worked on in the reading and writing process.

This paper presents an electrical study on logic functions with up to 4 inputs designed with a standard cell mapping and two automatically generated supergates methodologies. The results indicate that supergate-based designs reduce the average power in 84.4% of the studied cases while reducing area by 12.9%. Despite the supergate design increasing in average the circuit critical delay by 5.8%, it achieves better power-delay-product in 2823 (70.9%) of the 3982 studied logic functions. The reduction of logic levels is the main factor for gains obtained with supergates due to the glitch power reduction.

The technology scaling has boosted the importance and gravity of radiation faults. Hardening techniques are required to ensure a high level of reliability, mainly to the harsh critical applications. Hardware redundancy remains the most adopted option to deal with fault tolerance, mostly the TMR technique. However, the weakness of this technique is the voter circuit. This paper investigates the robustness of nineteen majority voter designs in the presence of a SET. The analysis explores critical diffusion areas and LET threshold. The results show designs with 3X difference in the number of critical diffusion areas and 6X in the LET threshold.

The aggressive technology scaling has significantly affected the circuit reliability. Several techniques have been explored to mitigate the scaling effects and guarantee a satisfactory reliability level. In this context, estimating circuit reliability is crucial and a challenge that has not yet been overcome. For decades, traditional reliability estimation techniques have used fixed logic gates reliability values. Recently, methods demonstrate that using fixed gate reliability values compromises the accuracy of the analysis. This work evaluates the impact of the estimated logic gate susceptibility in the reliability of several benchmarks circuits mapped with different sets of logic gates. The obtained results show a discrepancy in the reliability of the same circuit. However, the change in the reliability behavior may be considered the main contribution of this work. The utilization of fixed reliability values for logic gates provides reliability values inversely proportional to the number of gates in the circuit. The used approach captures the logical characteristics of the gates. The same circuit mapped with basic gates presents a difference in MTBF of 20%, while the one mapped with a complex set of gates is bigger than 70%.

Logic synthesis is a fundamental step in hardware design whose goal is to find structural representations of Boolean functions while minimizing delay and area. If the function is completely-specified, the implementation accurately represents the function. If the function is incompletely-specified, the implementation has to be true only on the care set. While most of the algorithms in logic synthesis rely on SAT and Boolean methods to exactly implement the care set, we investigate learning in logic synthesis, attempting to trade exactness for generalization. This work is directly related to machine learning where the care set is the training set and the implementation is expected to generalize on a validation set. We present learning incompletely-specified functions based on the results of a competition conducted at IWLS 2020. The goal of the competition was to implement 100 functions given by a set of care minterms for training, while testing the implementation using a set of validation minterms sampled from the same function. We make this benchmark suite available and offer a detailed comparative analysis of the different approaches to learning.

Detailed routing is one of the most time-consuming steps of physical synthesis of integrated circuits. Also, it is very challenging due to the complexity of the design rules that the router must obey. In this article, we present SmartDR, a detailed routing system that focuses on good design rule handling and fast runtime. To attend these objectives, we propose a novel pin access approach and a fast design rule aware A*-interval-based path search algorithm. The pin access method uses resource sharing ghost pin access paths with dynamic legalization check. We also propose a design rule check algorithm to detect thick metal shapes that are widely created using the proposed pin access method. The path search algorithm integrates design rule check on its core, handling many design rules that would not be possible to be solved by postprocessing. It is aware of the minimum area rule, the cut spacing of via cuts within the same path, and the via library. We also present a new technique to improve A*-based path search in detailed routing. The technique makes the path search algorithm aware of the global routing guides, accelerating the search. Using ISPD 2018 Contest benchmarks, our experiments show that our router is superior to the state-of-the-art routers that were also tested using the same benchmarks. Our router has presented, on average, 77.6% less runtime, 73.5% less design rule violations, with respect to Dr. CU 2.0, which is the better of the compared routers.

This paper presents a new transistor placement method applied to the ASTRAN EDA tool, an open-source solution for the automatic design of complex digital gates. Although it currently reaches an optimized solution through a Threshold Accepting approach, ASTRAN does not guarantee a minimum-width placement. In this paper, a method based on Boolean satisfiability is proposed, ensuring an optimal solution for the transistor placement task through modeling the problem into a set of Boolean variables and clauses aware of four design rule constraints. Experiments comparing the proposed method and the current ASTRAN placement technique have shown reductions in the layout area. Furthermore, our method achieved a significant improvement regarding runtime, an essential feature for designing digital circuits and systems on-demand.

This paper presents a study comparing complex gates that use Series-Parallel and Non-Series-Parallel associations, including the time-zero variability and the BTI impact. A comparison of 53 logical functions was performed, showing that the reduction in the number of transistors and area of NSP structures does not assure better power and timing results, with the SP structure gates presenting a smaller power. Structures built where both the pull-up and pull-down networks are optimized individually presented better results in average value and robustness to variability and aging.

New design methodologies are needed to improve the circuit robustness to deal with technology scaling issues. Traditional fault-tolerant approaches present severe overheads. Alternative solutions based on partial fault tolerance and fault avoidance are considered a possible solution to the reliability problem. An accurate evaluation of circuit reliability is fundamental to allow a reliability-aware automated design flow, where the synthesis tool could rapidly cycle through several circuit configurations to assess the best option. Most of the circuit reliability estimation methods use logic gate information as the starting point. The difference in logic gates reliability is neglected. This work proposes models capable of analyzing logic gates susceptibility in different abstraction levels. Three methods are proposed based on transistor arrangement, stick diagram, and layout of the logic gates. A 45nm standard cell library is used to validate the proposed methods. The achieved results are used to analyze ISCAS'85 benchmark circuit reliability. The obtained Mean Time Between Failures (MTBF) shows a considerable reduction of almost 50% compared to the values from traditional fixed logic gate reliability.

One approach to solve detailed routing is net-by-net using a fast A∗-based path search algorithm to handle long connections. Such path search algorithms usually rely on the manhattan distance to implement their heuristic function, providing a poor lower bound since the search is constrained by the global routing guide. This work proposes a new technique to provide a more realistic lower bound in this scenario. We precompute some lower bounds before the path search by applying a modified version of Dijkstra's algorithm on tunnels (sections of the global routing guide). This information is used during the search, reducing the runtime by 58% in average, in comparison to the classic manhattan distance, on ISPD 2018 benchmarks. We also show an improvement of our technique over existing work [10]. Our preprocessing method runtime is negligible, maximizing the benefit of using the improved heuristic function during the path search.

Secure triple track logic (STTL) is a circuit-level countermeasure to differential power analysis (DPA) attacks based on dual-rail precharge logic (DPL). STTL is robust to attacks due to the delay insensitive topology characteristic that avoids the glitches generated by the different path delays, before the logic gate inputs stabilize. However, the main STTL drawbacks are the validation of timing-robustness and the unbalanced and asymmetric transistors arrangement that result in variable internal capacitances and different internal paths to the current flow behaviors. The main contribution of this work is a new STTL-based topology called MT-BSTTL that combines multi-threshold with a set of circuit balancing improvements on capacitance, current paths, and fan-in, aiming to maximize the energy-efficiency while still preserving the side-channel attack-resistance. Three basic logic gates were implemented using the proposed strategy and other secure transistor topologies, all using the TSMC 40 nm technology. Results show that MT-BSTTL outperforms all state-of-the-art logic styles in terms of robustness against DPA attacks. Comparing to the baseline STTL, the proposed MT-BSTTL is, at least, 50% faster, has 53.5% higher energy-efficient, and it is 44% more robust, incurring in a 40% circuit area penalty.

The progressive downscaling of feature sizes increases the susceptibility to Single Event Effects in integrated circuits. As a manner to mitigate soft errors, solutions incur significant performance and area penalties, especially when a design with fault-tolerant structure is overprotected. Probabilistic methods such as Probabilistic Transfer Matrix and Signal Probability Reliability Multi-Pass are prone to multiple faults scenario to evaluate circuits reliability. However, it is necessary that the probabilistic matrices of the gates being accurate enough for this task. This paper proposes a method to evaluate gate failure rate considering faults in Layout-Level. This method can be used to enrich the probabilistic matrices creation taking into account the characteristics of the layout in order to evaluate gate reliability and the failure rate more precisely. Results show a reduction of 40% in the failure rate just choosing the best layout alternative for the same logic function.

The circuit reliability in nanometer technologies has become an important aspect of circuit design. Techniques to improve reliability usually increase project costs. To avoid overdesign, techniques to estimate circuit reliability are commonly used. These techniques usually explore probabilistic Matrices to compute the circuit reliability. The matrices used to represent logic functions are simplified do not taking into account the logic gate design. In this way, the main goal of this thesis is to propose a method capable of creating probabilistic matrices from logic gates layouts and then improve the accuracy of the reliability evaluation methods.

The path search problem is very common in computing. One of its applications is in the VLSI routing. Since most of the path search algorithms used today are old, their evaluation took place in out of date scenarios, such as small 2D grid graphs. Thus, this work presents some path search algorithms, as well as an experiment comparing them in a scenario similar to detailed routing of integrated circuits. The presented algorithms are Soukup's, A*, LCS* and Hetzel's. We used ISPD 2008 benchmarks and FastRoute4 in order to create the input for the detailed routing experiment. The results show that Hetzel's algorithm is faster than the compared algorithms, and since it is optimal, it is a better choice for a path search algorithm in detailed routing.

Recently, methods for switch network generation have gain relevance. The main goal of these techniques is to minimize the number of transistors in the logical arrangement. However, theses methods do not consider optimizations at layout level. In this paper, we propose a post-processing technique in a state-of-art method for network generation to improve some layout aspects such as area, delay, power and parasitic capacitance. Experiments performed over a well-known benchmark demonstrate that the proposed technique allows average gains of 7.48% and 8.48% in the cell area and wirelength, respectively. Electrical characterization results have also shown improvements for propagation delay, transition delay, leakage and switching power in 4.18%, 4.94%, 7.52% and 12.40%, in that order.

Double-gate devices, like independent-gate (IG) FinFET, have introduced new possibilities and challenges in synthesis of transistor networks. Existing factorization methods and graph-based optimizations are not actually the most effective way to generate optimized IG FinFET based networks because only reducing the number of literals in a given Boolean expression does not guarantee the minimum transistor count. This paper presents two novel methods aiming the minimization of the number of devices in logic networks. The first contribution is a method for defactoring Boolean expressions able to apply the conventional factorization algorithms together with IG FinFET particularities, so improving it. The second contribution is a novel graph-based method that improves even more transistor arrangements by exploiting enhanced nonseries-parallel associations. Experimental results shown a significant reduction in the size of transistor networks delivered by the proposed methods.

Transistor network optimization represents an effective way of improving VLSI circuits. This paper proposes a novel method to automatically generate networks with minimal transistor count, starting from an irredundant sum-of-products expression as the input. The method is able to deliver both series-parallel (SP) and non-SP switch arrangements, improving speed, power dissipation, and area of CMOS gates. Experimental results demonstrate expected gains in comparison with related approaches.

The transistor arrangement optimization is an effective possibility to improve VLSI design, especially when generating CMOS logic gates to be inserted in standard cell libraries. This paper addresses this issue and presents a new methodology to generate efficient transistor networks. Starting from an input ISOP, the proposed method is capable to deliver series-parallel and non-series-parallel arrangements with reduced transistor count. By applying the proposed approach, it is possible to achieve optimized transistor arrangements since greedy choices are avoided during part of the generation process. The performed experiments have demonstrated the efficiency of this methodology when comparing to other available techniques.

This paper introduces a new algorithm for Boolean factoring. The proposed approach is based on a novel synthesis paradigm, functional composition, which performs synthesis by associating simpler sub-solutions with minimum costs. The method constructively controls characteristics of final and intermediate functions, allowing the adoption of secondary criteria other than the number of literals for optimization. This multi-objective factoring algorithm presents interesting features and advantages when compared to previous works.

This paper proposes a new method to estimate static power dissipation in digital circuits by evaluating simultaneously subthreshold and gate oxide leakage currents. The estimation method is performed over logic cells, including CMOS complex gates with multi-level series-parallel devices. Experimental results have been carried out on different fabrications processes, and good correlation with HSPICE simulator was obtained at cell and circuit levels. The algorithm presents a speed up of 80x when compared to HSPICE.

This paper proposes a library-free technology mapping algorithm to reduce delay in combinational circuits. The algorithm reduces the overall number of series transistors through the longest path, considering that each cell network has to obey to a maximum admitted chain. The number of series transistors is computed in a Boolean way, reducing the structural bias. The mapping algorithm is performed on a Directed Acyclic Graph (DAG) description of the circuit. Preliminary results for delay were obtained through SPICE simulations. When compared to the SIS technology mapping, the proposed method shows significant delay reductions, considering circuits mapped with different libraries.