In-Field Test (IFT) has for long relied on using Built-in self-test (BIST). This involves power-on, power-off and testing during device operation. Hyper-scalar datacenters that often-run large-scale AI/ML applications need to run periodic testing of the device in-field. This is necessary to prevent interruptions caused by Silent Data Corruption (SDC) and various other failures. The objective is to do so, without adding extra BIST hardware for logic test. For this, targeted portions of the device must be accessible for testing, while the rest of the device is running in functional mode. This poster explores a method to test the device In-field using In-System Embedded Deterministic Test (IS-EDT) patterns delivered through Streaming Scan Network (SSN) for on-chip distribution of the patterns to the cores. The In-System Test Controller (ISTC) runs IS-EDT patterns and can also use an IJTAG network to run BIST capabilities. The poster also spells out the merits and challenges of using SSN only at the chip-top level with EDT-only cores. The implementation follows the hierarchical approach - that is patterns are generated at the core level and re-targeted to the top level.

Recent studies of silent data errors (SDEs) in mega-scale datacenters indicate that SDEs are caused by small delay defects that escaped detection by manufacturing tests or occurred during the lifetime of the system. A small delay defect is detected by a test that propagates a transition through one of the longest paths that includes the defect site. Once the path is selected, for every gate or cell on the path, ATPG assigns off-path input values to enable the propagation of a transition through the path. For complex gates, such as AOI and XOR, there are multiple sets of possible assignments (or input stimuli) that the ATPG can use, with substantially different propagation delays. Existing test generation procedures do not consider these differences in propagation delays once a path is selected. We propose a new approach to ATPG for small delay defects, called Timing Verification Test or TVT, that selects the off-path input values to maximize the delay of the path. The tests produced by TVT result in path delays that are significantly higher than those obtained when off-path input values are selected arbitrarily by the ATPG if they are not mandated by the propagation conditions. TVT also considers different PVT corners that affect the selection of the longest paths. Experimental results for an industrial core show that TVT increases the path delays by up to 15.91% for a set of the longest paths needed to detect small cell-aware delay faults at different PVT corners.

The adverse effects of silent data errors (SDEs) on the operation of large data centers have been reported recently by hyper-scalar companies. SDEs tend to be elusive and are difficult to detect until they affect a particular application after the IC has been deployed in-field. Although the cause of SDEs ranges from manufacturing test escapes and design marginalities to design bugs, experimental data from the industry largely indicate that SDEs can be traced back to timing related issues that become more severe with aging and depend on the operating conditions of process, voltage and temperature (PVT). This paper describes a complete framework for monitoring the timing related issues under different operating conditions for test and functional operation. The framework has three components. The first component is a procedure for the identification of the longest paths that are prone to delay failures under different PVT corners. The second component is a programmable slack monitor design that monitors the changes in path delays within a detection window, and produces an alarm when a path is close to failure, with proximity to failure being a programmable feature. The third component is a procedure that determines the placement of the monitors in the design. Experimental results for an industrial design demonstrate the trade-offs related to the placement of monitors and the scenarios under which the monitors raise alarms.

Recently the semiconductor industry has been alerted by hyperscaler companies reporting impact of field errors in megascale datacenters. They tend to be elusive and very difficult to detect until they affect a particular application several days or months after the IC has been deployed in a fleet. Although the cause of such errors can be manifold, ranging from test escapes and design marginalities to design bugs, there is a consensus across the industry that they usually can be traced back to timing-related issues, as the performance of transistors changes over time or at certain environmental conditions while running specific software workloads. While there is ongoing work to study some of those defects and to explore techniques preventing such post-manufacturing test escapes, it also highlights the need for IC monitoring so that such defects are detected in the field, thereby reducing application failures. The paper demonstrates a successful application of the Streaming Scan Network technology to run in-fleet deterministic scan test on an ultralarge industrial multi-chiplet design at Amazon Web Services (AWS) cloud computing platform. One of the key advantages of the presented technology is its ability to use the same infrastructure to perform both manufacturing and in-field tests. A silicon implementation along with test power analysis are also presented.

VLSI design flows improve design parameters (performance, power, area, and testability) iteratively. Whereas the “shift left” trend implies that changes at the RTL are preferred for improving the design, it is sometimes necessary to make gate-level changes, e.g., because of layout changes or ECO. In an iterative design flow, repeated ATPG to evaluate the testability of a design after design changes have been made creates a bottleneck. The goal of this article is to address this bottleneck considering two-cycle tests for transition faults. The test generation procedure described in third article transforms an LOC test set generated for an earlier version of the design into an LOC test set for a new version without repeating the entire test generation process. To enable the transformation, it is necessary to find a mapping between the inputs and outputs of the earlier and new versions of the design, taking into consideration that RTL resynthesis may produce a new gate-level netlist, with new signal names and different input and output orders. To address two-cycle tests, the mapping is performed over two time frames of the design. Experimental results for industrial circuits with changes made at the RTL as well as gate-level demonstrate significant runtime gains with the test generation procedure described in this article.

We need to address the multifaceted challenges about silicon and system quality throughout the life cycle of silicon-based systems, spanning from design, production to in-field deployment. Innovations spanning across various parts of the silicon ecosystem are needed. In this session we invited industry experts to discuss technical trends and challenges in semiconductor industry driving a pressing need of more innovations in the emerging field of silicon lifecycle management (SLM). They will present the state-of-the-art SLM methodologies and share their perspectives of this emerging field and thoughts of future R&D directions.

A typical VLSI design flow is iterative, implying that performance, power, area and testability are improved iteratively. With the shift left paradigm, most of the changes made to a design, including to a large extent changes to address testability, occur at the RTL. Test generation is an exception with a gate level netlist being required by ATPG tools. Within an iterative flow, repeated ATPG to reevaluate the testability of a design after its RTL has been changed becomes a bottleneck. To address this bottleneck, the test generation process needs to transform a test set generated for an earlier version of the design into a test set for a new version without repeating the entire test generation process. To enable the transformation, it is necessary to find a mapping between the inputs and outputs of the earlier and new versions of the design. The main contribution of the paper is to compute such a mapping after RTL changes and resynthesis produce a new gate level netlist, where signal names may have changed, new signals may have been introduced, and signals that existed earlier may have been removed. Experimental results for industrial circuits with changes made at the RTL show an average of 5-fold reduction in test generation time.

This paper describes a fast test generation process for digital circuits that exhibit extensive structural similarity. The property of structural similarity can be seen in circuits that are subjected to engineering change order (ECO), circuits that are modified during place and route, circuits subjected to retiming, and circuits with multiple similar cores. The goal of the paper is to determine the testability of a circuit (circuit2) given a test set for a structurally similar circuit (circuit1). This is achieved by transforming a test set generated for circuit1 into a test set for circuit2 as efficiently as possible, without repeating the entire test generation process. The process described in the paper starts with a structural analysis of circuit1 and circuit2 to obtain a mapping between their inputs and outputs. The mapping is used for transforming test patterns from circuit1 into test patterns for circuit2. The experiments conducted on industrial designs show an average of more than 10-fold reduction in runtime, compared with running the entire test generation process for circuit2.

Contemporary and emergent automotive systems are heavily populated by complex integrated electronics. The number of safety-critical devices used in advanced driver-assistance systems or autonomous vehicles is growing with high-end models containing hundreds of embedded microcontrollers. Achieving functionally safe automotive electronics requires test solutions that might be costly to engineer. Therefore, to address challenges posed by high-quality and long-term reliability requirements, this article presents low-cost test pattern generation schemes for a scan-based hybrid logic BIST of automotive ICs. It may allow one to optimize test coverage and test time during in-system test applications. The first presented technique deploys a seed-flipping PRPG to periodically complement PRPG stages in a methodical tree-traversal manner. The second scheme is based on a seed-sorting approach that allows additional tradeoffs between test data volume and test coverage. As shown in this article, the proposed schemes can be easily integrated with a test compression environment and deployed in different modes of in-system testing, such as key-off, key-on, and periodic (incremental) online tests. Experimental results obtained for automotive designs and reported herein show improvements in test quality over conventional logic BIST schemes.

As automobiles become increasingly computerized, the safety requirement of hundreds of ICs used in a car is growing rapidly. Testing of such automotive ICs is more stringently than testing other ICs because the quality, reliability and functional safety of such ICs are extremely important as they are directly related to human lives. Many standards such as ISO 26262 are used to guide for high quality and long-term reliability driven by functional safety requirements. In this industry session, we invite 3 experts from IC design and EDA companies. They share their experiences with many case studies, and focus on different aspects of automotive testing, online monitoring, reliability and in-system functional safety.

Hybrid test schemes comprising on-chip test compression and logic built-in self-test are expected to play a pivotal role in the design of new integrated circuits and delivering high quality tests. As architectural differences between these two paradigms are gradually blurring, and both schemes efficiently share test logic, they become more vulnerable to unknown (X) states whose sources vary from uninitialized memory elements to unwrapped-for-test analog modules. Typically, X values degrade test results, and thus test response compaction schemes must be duly protected. This article presents maXpress-an X-tolerant tunable compactor deploying a new scan chain selection mechanism capable of completely masking X states, as required by many in-system or one-directional streaming test applications, within redefinable groups of scan chains and designated scan shift cycles. The proposed scheme is also supporting separate observation scan chains that, in contrast to conventional scan, capture faulty effects every shift cycle, while their content is gradually shifted into a compactor shared with the remaining chains. In addition to a new layout-friendly architecture, the article proposes algorithms to automate maXpress control settings based on scan chain selection rules deployed to suppress X states. Experimental results obtained for industrial designs show feasibility and efficiency of the proposed scheme altogether with actual impact of X-masking on a resultant test coverage and test pattern counts.

As cars become increasingly computerized and their safety functions evolve rapidly, the number of complex safety-critical components deployed in advanced driver assistance systems or autonomous vehicles is rising dramatically with high-end models containing hundreds of embedded microcontrollers. These integrated circuits must adhere to stringent requirements for high quality and long-term reliability driven by functional safety standards. This requires test solutions that address challenges posed by automotive systems. This article presents a scan-based test scheme optimizing test time and area overhead during manufacturing and in-system test of automotive electronics. The proposed scheme deploys observation test points that capture the faulty effects in every shift cycle into separate observation scan chains. To reduce area overhead, the scheme enables the sharing of flip-flops among control points. It is also shown how test points enhance test coverage (TC) in the presence of cascaded clock gaters. Finally, processing challenges when fault simulating every scan shift cycle to determine TC are addressed. Experimental results obtained for contemporary automotive designs and reported herein show significant improvements in test quality over traditional solutions.

As the use of electronic components grows rapidly in the automotive industry, the number of complex safety-critical devices used in advanced driver assistance systems or autonomous cars is rising with high-end models containing more than 200 embedded microcontrollers. Achieving functionally safe automotive electronics requires test solutions that address challenges posed by high quality and long-term reliability requirements mandated, for example, by the ISO 26262 standard. The paper presents test pattern generation schemes for a scan-based logic BIST optimizing test coverage and test time during in-system test applications for automotive ICs. As a part of overall safety, they help in ensuring reliable operations of vehicle's electronics throughout their lifecycles. The proposed schemes can be deployed in different modes of in-system testing, including key-off, key-on, and periodic (incremental) online tests. Experimental results obtained for automotive designs and reported herein show improvements in test quality over conventional logic BIST schemes.

There is a growing number of integrated circuits that deploy hybrid test schemes combining on-chip test compression with logic BIST, with both techniques working synergistically to deliver high quality tests. As their architectural differences are gradually blurring, and both schemes efficiently share test logic, they become more vulnerable to unknown (X) states whose sources vary from uninitialized memory elements to unwrapped-for-test analog modules. Typically, X values degrade test results, and thus test response compaction schemes must be duly protected. This paper presents maXpress – an X-tolerant programmable compactor deploying a new scan chain selection mechanism capable of completely (as required by many in-system test applications) masking X states within redefinable groups of scan chains and designated scan shift cycles. In addition to the new architecture, the paper proposes an algorithm to automate maXpress control settings based on scan chain selection rules deployed to suppress X states. Experimental results obtained for a variety of industrial designs show feasibility and efficiency of the proposed scheme altogether with actual impact of X-masking on a resultant test coverage and test pattern counts.

This paper proposes an innovative design methodology for layout-friendly decompressor used in EDT compression architecture. A segmented decompressor architecture is proposed, in which each segment drives a subset of scan chains. The EDT input channel injectors are carefully selected to maximize the encoding capacity for all scan chains. Experimental results with several large industrial designs demonstrate that using the proposed technology, the routing congestion introduced by EDT decompressor is reduced significantly with negligible impact on test coverage and improved pattern count.

As the automotive industry enters a period of rapid evolution changing the way cars are designed and produced, the number of complex safety-critical components deployed in advanced driver assistance systems or autonomous vehicles is progressively rising with high-end models containing around 120 MCUs. These integrated circuits must adhere to stringent requirements for high quality and long-term reliability driven by functional safety standards. This requires test solutions that address challenges posed by automotive electronics. This paper presents Stellar BIST-a next generation compression scheme for in-system automotive test. The proposed solution can work with any sequential test compression. It builds on a finding that certain clusters of test vectors are capable of detecting many random-resistant faults, where a cluster consists of a parent (base) pattern and its transformed derivatives. Stellar BIST involves generating vectors based on simultaneous and multiple complements of scan slices of encodable parent patterns. The multiple complements are also skewed between successive patterns to diversify the resultant tests. The new scheme elevates compression to values unachievable through conventional reseeding-based solutions and provides significant tradeoffs between storage requirements and test application time, critical for in-system automotive applications. The experimental results obtained for industrial designs and different fault models illustrate feasibility of the proposed test scheme and are reported herein.

As cars become increasingly computerized and their safety functions are evolving rapidly, the number of complex safety-critical components deployed in advanced driver assistance systems or autonomous vehicles is progressively rising with high-end models containing more than a hundred embedded microcontrollers. These integrated circuits must adhere to stringent requirements for high quality and long-term reliability driven by functional safety standards. This requires test solutions that address challenges posed by automotive electronics. The paper presents a scan-based LBIST scheme optimizing test time and area overhead during in-system test applications for automotive ICs. It ensures highly reliable operations of ICs for the duration of their lifespan. The proposed scheme works with observation test points that capture faulty effects every shift cycle into separate observation scan chains. To reduce area overhead, the scheme takes advantage of a procedure allowing one to share flip-flops among control points. It is also shown how test points can enhance test coverage in the presence of cascaded clock gaters. Finally, processing challenges when fault simulating every scan shift cycle to determine observed faults are addressed. Experimental results obtained for contemporary automotive designs and reported herein show significant improvements in quality of test over traditional BIST schemes.

Logic built-in self-test (LBIST) is now increasingly used with on-chip test compression as a complementary solution for in-system test, where high quality, low power, low silicon area, and most importantly short test application time are key factors affecting ICs targeted for safety-critical systems. Test points, common in LBIST-ready designs, can help to reduce test time and the overall silicon overhead so that one can get desired test coverage with the minimal number of patterns. Typically, LBIST test points are dysfunctional when enabled in an ATPG-based test compression mode. Similarly, test points used to reduce ATPG pattern counts (PCs) cannot guarantee desired random testability. In this paper, we present a hybrid test point technology designed to reduce deterministic PCs and to improve fault detection likelihood by means of the same minimal set of test points. The hybrid test points are subsequently deployed in a scan-based LBIST scheme addressing stringent test requirements of certain application domains such as the automotive electronics market. These requirements, largely driven by safety standards, are met by significantly reducing test application time while preserving the high fault coverage. The new scheme is a combination of pseudorandom test patterns delivered in a test-per-clock fashion through conventional scan chains and per-cycle-driven hybrid observation test points that capture faulty effects every shift cycle into dedicated scan chains. Their content is gradually shifted into a compactor shared with the remaining chains that deliver responses once a test pattern has been shifted-in. Experimental results obtained for industrial designs confirm feasibility of the new schemes, and they are reported herein.

With the growing number of very complex safety-critical components used in advanced driver assistance systems and autonomous vehicles, integrated circuits in this area must adhere to stringent requirements for high quality and long-term reliability driven by functional safety standards. This, in turn, requires advanced test solutions that have to respond to challenges posed by automotive parts. This paper presents Stellar BIST - a deterministic two-level compression scheme for in-system automotive test. The proposed solution seamlessly integrates with any sequential test compression scheme and takes advantage of the fact that certain clusters of test vectors detect many random-resistant faults where a cluster consists of a parent pattern and its transformed derivatives. Stellar BIST involves generating vectors based on simultaneous and multiple complements of scan slices of encodable parent patterns. The multiple complements are also skewed between successive patterns to diversify the resultant tests. The new scheme elevates compression to values unachievable through conventional reseeding-based solutions and provides significant trade-offs between area and time, critical for in-system automotive applications. Experimental results obtained for large industrial designs with stuck-at and transition faults illustrate feasibility of the proposed test scheme and are reported herein.

Growing reverse-engineering attempts to steal or violate a design intellectual property (IP), or to identify the device technology in order to counterfeit integrated circuits (ICs), raise serious concerns in the IC design community. As the information derived from these practices can be used in a number of malicious ways, various active techniques have been proposed and deployed to protect IP, of which logic locking is a vital part. It allows inserting certain gates in a circuit's data path to lock outputs to fixed logic values, if a wrong unlocking key is applied. This paper demonstrates that test points-industry-proven design-for-test technology used primarily to enhance the overall design testability-can also be reused in the mission mode to lock the circuit, and thus to improve the hardware security against IP piracy. In particular, it is shown that test points can facilitate the hiding of design functionality from adversaries. As a result, not only is the overall design testability improved, but also effective protection against piracy through unauthorized excess production and other forms of IP theft is ensured. Experimental results on industrial designs with test points demonstrate that the proposed scheme is effective in achieving a desired degree of hardware obfuscation.

This paper presents a novel low-area scan-based logic built-in self-test (LBIST) scheme that addresses stringent test requirements of certain application domains such as the fast-growing automotive electronics market. These requirements, largely driven by safety standards, are met by significantly reducing test application time while preserving the high fault coverage of conventional BIST schemes. Alternatively, one may consider applying a much larger number of vectors within the same time interval. Although the new scheme may resemble traditional BIST logic, it is a combination of pseudorandom test patterns delivered in a test-per-clock fashion through conventional scan chains and per-cycle-driven hybrid test points that creates this new synergistic LBIST paradigm. The hybrid observation points, inserted at the most suitable locations, capture faulty effects every shift cycle into dedicated flip-flops that form separate scan chains. Their content is gradually shifted into a compactor, which is shared with the remaining scan chains that still deliver test responses captured once the entire test pattern has been shifted-in. Experimental results obtained for industrial designs illustrate feasibility of the proposed BIST scheme in terms of test time, test coverage, and area overhead, and they are reported herein.

There is mounting evidence that automatic test pattern generation tools capable of producing tests with high coverage of defects occurring in the large semiconductor nanometer designs unprecedentedly inflate test sets and test application times. A design-for-test technique presented in this paper aims at reducing deterministic pattern counts and test data volume through the insertion of conflict-aware test points. This methodology identifies and resolves conflicts across internal signals allowing test generation to increase the number of faults targeted by a single pattern. This is complemented by a method to minimize silicon area needed to implement conflict-aware test points. The proposed approach takes advantage of the conflict analysis and reuses functional flip-flops as drivers of control points. Experimental results on industrial designs with on-chip test compression demonstrate that the proposed test points are effective in achieving, on average, an additional factor of 2×-4× compression for stuck-at and transition patterns over the best up-to-date results provided by the embedded deterministic test (EDT)-based regular compression.

Recent reverse-engineering attempts to steal a competitive design intellectual property (IP) or to identify the device technology in order to counterfeit integrated circuits (ICs) have raised serious concerns in the IC design community. This paper demonstrates that test points - industry-proven design-for-test technology used to enhance the overall design testability - can also be deployed in the mission mode to obfuscate the circuit's structure, and thus to improve the hardware security against reverse engineering, IC cloning, and IP theft. In particular, it is shown how test points can facilitate the hiding of design functionality from adversaries. As a result, not only the overall design testability is improved, but also effective protection against reverse engineering and other forms of attacks is ensured.

Conflict-aware test points, introduced recently, facilitate significant reductions in deterministic test pattern counts. However, dedicated flip-flops driving control points increase test logic area. This paper presents a method to minimize silicon area needed to implement conflict-aware test points by reusing functional flip-flops as drivers of control points. Conflict analysis is applied during the test point selection process, and ATPG verification is run for every potential candidate. Experimental results show that functional flip-flops can be reused as drivers for more than 90% of the control points with the average of 5% penalty in pattern count increase as compared to methods using only dedicated flip-flops. After replacing dedicated flip-flops with functional flip-flops, conflict-aware test points can still achieve remarkable pattern count reductions.

Logic built-in self-test (LBIST), originally introduced for board, system, and in-field tests, is now being increasingly used with on-chip test compression. This hybrid approach allows LBIST to become a complementary solution for in-system test, where high quality, low power, low silicon area, and most importantly short test application time are key factors affecting ICs that are targeted for safety-critical and automotive systems. Test points are common in BIST-ready designs where they play a key role in reducing both test application time given a test coverage goal and the overall silicon overhead so that one can get a desired coverage with the minimal number of patterns. Unfortunately, these test points are typically dysfunctional when enabled in an ATPG-based test compression mode. Similarly, test points used to reduce ATPG-based test pattern counts cannot guarantee desired random testability. Incompatibility of both types of test points has motivated research presented in this paper. We present a novel hybrid test point technology designed to both reduce deterministic pattern counts and improve fault detection likelihood by means of the same minimal set of test points. Experimental results obtained for large industrial designs illustrate feasibility of the proposed hybrid test points and are reported herein.

This paper presents a new method to design digital circuits for low pattern counts, one of the key factors shaping cost-effective VLSI test schemes. The method identifies the largest conflicts between internal signals that prevent efficient test compaction in ATPG. These locations are modified by inserting conflict-reducing test points (CRTP) to significantly reduce the ATPG-produced pattern counts. Experimental results obtained for large industrial designs with on-chip test compression demonstrate, on average, 3x -- 4x reduction in stuck-at and transition patterns and 3x shorter ATPG times.

The introduction of FinFET technology has accelerated the adoption of patterns that target cell internal defects such as cell-aware tests. Even though cell-aware tests can replace stuck-at and transition patterns from the screening point of view, we have to address the increase in test data volume. This combined with the growing gate counts enabled by new technology nodes is driving the need for even greater compression levels. In this paper, we present a novel test points technology designed to reduce deterministic pattern counts for cell-aware tests. The technology is based on identification and resolution of conflicts across internal signals allowing ATPG to significantly increase the number of faults targeted by a single pattern. Experimental results on a number of industrial designs with test compression demonstrate that the proposed test points are effective in achieving, on average, a 3×–4× multiplicative increase in compression for 1-cycle and 2-cycle cell-aware patterns.

Provides an abstract for each of the presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings.

This paper introduces a novel test data compression scheme, which is primarily devised for low-power test applications. It is based on a fundamental observation that in addition to low test cube fill rates, a very few specified bits, necessary to detect a fault, are actually irreplaceable, whereas the remaining ones can be placed in alternative locations (scan cells). The former assignments are used to create residual test cubes and, subsequently, test templates. They control a power-aware decompressor and guide automatic test pattern generation to produce highly compressible test patterns through finding alternative assignments. The proposed approach reduces, in a user-controlled manner, scan shift-in switching rates with minimal hardware modifications. It also elevates compression ratios to values typically unachievable through conventional low-power reseeding-based solutions. Experimental results obtained for large industrial designs illustrate feasibility of the proposed test scheme and are reported herein.

This paper presents several techniques employed to resolve problems surfacing when applying scan bandwidth management to large industrial multicore system-on-chip (SoC) designs with embedded test data compression. These designs pose significant challenges to the channel management scheme, flow, and tools. This paper introduces several test logic architectures that facilitate preemptive test scheduling for SoC circuits with embedded deterministic test-based test data compression. The same solutions allow efficient handling of physical constraints in realistic applications. Finally, state-of-the-art SoC test scheduling algorithms are rearchitected accordingly by making provisions for: 1) setting up time-effective test configurations; 2) optimization of SoC pin partitions; 3) allocation of core-level channels based on scan data volume; and 4) more flexible core-wise usage of automatic test equipment channel resources. A detailed case study is illustrated herein with a variety of experiments allowing one to learn how to tradeoff different architectures and test-related factors.

This paper describes a low-power (LP) programmable generator capable of producing pseudorandom test patterns with desired toggling levels and enhanced fault coverage gradient compared with the best-to-date built-in self-test (BIST)-based pseudorandom test pattern generators. It is comprised of a linear finite state machine (a linear feedback shift register or a ring generator) driving an appropriate phase shifter, and it comes with a number of features allowing this device to produce binary sequences with preselected toggling (PRESTO) activity. We introduce a method to automatically select several controls of the generator offering easy and precise tuning. The same technique is subsequently employed to deterministically guide the generator toward test sequences with improved fault-coverage-to-pattern-count ratios. Furthermore, this paper proposes an LP test compression method that allows shaping the test power envelope in a fully predictable, accurate, and flexible fashion by adapting the PRESTO-based logic BIST (LBIST) infrastructure. The proposed hybrid scheme efficiently combines test compression with LBIST, where both techniques can work synergistically to deliver high quality tests. Experimental results obtained for industrial designs illustrate the feasibility of the proposed test schemes and are reported herein.

The paper presents a high-speed serial interface between external tester and Embedded Deterministic Test (EDT) compression logic hosted by SoC designs. With only a single bidirectional link, the system is capable of feeding distributed heterogeneous cores with hundreds of test channels. Moreover, it synergistically supports EDT bandwidth management to improve the overall test performance. A detailed study indicates a high potential of the serial EDT approach to handle large multicore SoC designs by deploying only a single serial interface and completing the entire test for stuck-at faults in less than one second. Experiments conducted with the help of FPGA -- based evaluation platform confirm feasibility and a high effectiveness of the proposed solution.

On-chip test compression has quickly established itself as one of the mainstream design-for-test (DFT) methodologies. It assumes that a tester delivers test patterns in a compressed form, and on-chip decompressors expand them into actual data loaded into scan chains. This paper presents a new and comprehensive method to boost performance of sequential test compression and ATPG operations. The approach is primarily aimed at reducing CPU time associated with generating and compressing test patterns. It prevents ATPG from assigning specified values to many inputs in order to cut down a time-consuming backtracking process needed to resolve conflicts leading to compression aborts. The proposed scheme efficiently combines test compression constraints with ATPG. Experimental results obtained for industrial designs illustrate feasibility of the proposed scheme and are reported herein.

The paper presents a novel test data compression scheme. The invention follows from a fundamental observation that in a typical test cube only a small portion of the specified positions are necessary to detect a fault, and most of the remaining ones have many alternatives. The necessary assignments are used to form test templates which both control a decompressor to guarantee the necessary assignments and guide ATPG to find alternative assignments to produce highly compressible test cubes. The proposed approach synergistically elevates compression ratios to values typically unachievable through conventional reseeding-based solutions. It also reduces, in a user-controlled manner, switching rates in scan chains with minimal hardware modification. Experimental results obtained for large industrial designs illustrate feasibility of the proposed test scheme and are reported herein.

Low-power testing has become a need for modern designs due to rapid increasing of power density with further shrinking of feature size into nanoscale designs. In spite of low-power design efforts and low-power ATPG adopted in common test flows, excessive power dissipation and instant peak current cannot be necessarily avoided during test application. There is a need for fast peak power detection for test vectors. The test industry lacks such efficient solution. In this work, we propose a fast test power analysis methodology. By reading and processing layout data and other supporting files such as parasitic files, the proposed analysis engine performs a simplified power grid analysis with layout partition and provides following power results for each test cycle: switching activity, absolute power, hot spot contour map, absolute current estimation on power pads. The proposed flow was verified on industry designs and proved to be very efficient than using commercial power sign-off solutions for test power analysis.

Due to a production error, an incorrect figure was used for Fig. 8 on p. 1781 in the above paper (ibid., vol. 32, no. 11, pp. 1776-1786, Nov. 2013). The correct figure is presented here.

This paper describes a new programmable low power test compression method that allows shaping the test power envelope in a fully predictable, accurate, and flexible fashion by adapting the existing logic BIST infrastructure. The proposed hybrid scheme efficiently combines test compression with logic BIST, where both techniques can work synergistically to deliver high quality test. Experimental results obtained for industrial designs illustrate feasibility of the proposed test scheme and are reported herein.

The paper discusses practical issues involved in applying scan bandwidth management to large industrial system-on-chip (SoC) designs deploying embedded test data compression. These designs pose significant challenges to the channel bandwidth management methodology itself, flow, and tools. The paper introduces several test logic architectures that facilitate preemptive test scheduling for SoC circuits with EDT-based test data compression. Moreover, some recently proposed SoC test scheduling algorithms are refined accordingly by making provision for (1) setting up test configurations minimizing test time, (2) optimization of SoC pin allocation based on scan data volume, and (3) handling physical constraints in realistic applications. Detailed presentation of a case study is illustrated with a variety of experiments that allow one to learn how to tradeoff different architectures and test scheduling.

This paper presents novel methods of reducing test time and enhancing test compression for system-on-chip (SoC) designs armed with embedded deterministic test (EDT)-based compression logic. The ability of the proposed scheme to improve the encoding efficiency and test compression, while reducing test application time, is accomplished by appropriate selecting and laying out automatic test equipment channel injectors of every single core EDT-based decompressor as well as appropriate bandwidth management of the entire test procedure combined with new control data optimization techniques. The efficacy of the proposed scheme is validated through experiments on several industrial SoC designs and is reported herein.

This paper describes a low power programmable generator capable of producing pseudorandom test patterns with desired toggling levels and enhanced fault coverage gradient compared to best-to-date BIST-based PRPGs. We introduce a method to automatically select several controls of the generator allowing easy and precise tuning. The same technique is subsequently employed to deterministically guide the generator toward test sequences with improved fault-coverage-to-pattern-count ratios. Experimental results obtained for industrial designs illustrate feasibility of the proposed test scheme and are reported herein.

This paper presents preemptive test application schemes for system-on-a-chip (SoC) designs with embedded deterministic test-based compression. The schemes seamlessly combine new test data reduction techniques with test scheduling algorithms and novel test access mechanisms devised for both input and output sides. In particular, they allow cores to interface with automatic test equipment through an optimized number of channels. They are well suited for SoC devices comprising both nonisolated cores, i.e., blocks that occasionally need to be tested simultaneously, and completely wrapped modules. Experimental results obtained for large industrial SoC designs illustrate feasibility of the proposed test application schemes and are reported herein.

In this paper we examine several embedded low power test schemes that we have proposed over the last few years. These solutions are aimed at reducing the switching activity during all scan-based test operations, particularly including those developed for BIST or deployed to perform on-chip test data compression.

This paper presents a new BIST-based fault diagnosis scheme for non-march tests of complexity O(n^2). It can be used to identify failures in embedded memory arrays using galloping pattern tests. The proposed solution employs scalable and flexible logic to record test responses, with no negative impact on at-speed test. It enables recording of responses produced by failures hard to handle by conventional march tests. This, in turn, allows accurate isolation of memory failures during off-line processing.

This paper presents a study addressing the challenge of interfacing automatic test equipment (ATE) with on-chip decompression logic deployed by system-on-chip designs or modular decompression environments. The ability of the proposed scheme to improve the encoding bandwidth by reusing groups of scan chains for test data storage has been measured on industrial designs and is reported herein.

The paper presents a new channel allocation method for higher Embedded Deterministic Test (EDT) compression in SoC designs comprising isolated cores. It employs a test data reduction technique, which allows cores to interface with ATE through an optimized number of channels. This feature is subsequently used by a new test scheduling and test access mechanisms devised for both the input and output sides. Experimental results obtained for large industrial SoC designs illustrate feasibility of the proposed test application scheme and are reported herein.

The embedded deterministic test-based compression uses cube merging to reduce a pattern count, the amount of test data, and test time. It gradually expands a test pattern by incorporating compatible test cubes. This paper demonstrates that compression ratios can be order of magnitude higher, if the cube merging continues despite conflicts on certain positions. Our novel solution produces test clusters, each comprising a parent pattern and a number of its derivatives obtained by imposing extra bits on it. In order to load scan chains with patterns that feature original test cubes, only data necessary to recreate parent patterns as well as information regarding locations and values of the corresponding conflicting bits are required. A test controller can then deliver tests by repeatedly applying the same parent pattern, every time using a different control pattern to decide whether a given scan chain receives data from the parent pattern, or another pattern is used instead to recover content of the original test cube. Compression of incompatible test cubes preserves all benefits of continuous flow decompression and offers compression ratios of order 1000× with encoding efficiency much higher than 1.0. We also demonstrate that test clusters make it possible to deliver test patterns in a flexible power-aware fashion. This framework achieves significant reductions in switching activity during scan loading as well as additional test data volume reductions due to encoding algorithms employed to compress parent and control vectors.

This paper presents a built-in self-test (BIST)-based scheme for fault diagnosis that can be used to identify permanent failures in embedded read-only memories. The proposed approach offers a simple test flow and does not require intensive interactions between a BIST controller and a tester. The scheme rests on partitioning of rows and columns of the memory array by employing low cost test logic. It is designed to meet requirements of at-speed test thus enabling detection of timing defects. Experimental results confirm high diagnostic accuracy of the proposed scheme and its time efficiency.

The paper presents a new power-aware test scheme compatible with a newly proposed test compression environment based on deterministic clustering of test cubes with conflicts. The key contribution is a flexible test application framework that achieves significant reductions in switching activity during scan loading by means of a tri-modal test data decompressor.

The paper presents a preemptive test application scheme for system-on-chip (SoC) designs with EDT-based compression. It seamlessly combines a new test data reduction technique with a test scheduling algorithm and a novel test access mechanism. It is particularly well suited for SoC devices comprising non-isolated cores, i.e., blocks that occasionally need to be tested simultaneously.

This paper presents a novel low capture power test scheme integrated with EDT (Embedded Deterministic Test) environment. The key contribution of this paper is to generate test vectors that in capture mode mimic functional operation from switching activity point of view. Experimental results presented for industrial circuits demonstrate the effectiveness of the proposed method.

Unknown (X) states are increasingly often identified as having potential for rendering semiconductor tests useless. One of the key requirements for a reliable test response compactor is, therefore, to preserve observability of any scan cell for a wide range of X-profiles while maintaining very high-compaction ratios, providing ability to detect a variety of failures found in real silicon, and assuring design simplicity. We have proposed a fully X-tolerant test response compaction scheme which is based on a flexible scan chain selection mechanism. This new approach delivers extremely high compression of test results by observing that X states are typically not randomly distributed in test responses. Identical or similar patterns of correlated X states let the proposed scheme reduce the size of a scan chain selector and the amount of test data used to control it. It handles, moreover, a wide range of unknown state profiles such that all X states, including those being clustered and of high density, are suppressed in a per-cycle mode without compromising the test quality.

Embedded memories are increasingly identified as having potential for introducing new yield loss mechanisms at a rate, magnitude, and complexity large enough to demand major changes in fault diagnosis techniques. In particular, time-related or complex read faults that originate in the highest density areas of semiconductor designs require new methods to diagnose more complex faults affecting large groups of memory cells. This paper presents a built-in self-test (BIST)-based fault diagnosis scheme that can be used to identify a variety of failures in embedded random-access memory arrays. The proposed solution employs flexible test logic to record test responses at the system speed with no interruptions of a BIST session. It offers a simple test flow and enables detection of time-related faults. Furthermore, the way test responses are processed allows accurate and time-efficient reconstruction of error bitmaps. The proposed diagnostic algorithms use a number of techniques, including discrete logarithm-based counting with ring generators acting as very fast event counters and signature analyzers. Experimental results confirm high diagnostic accuracy of the proposed scheme and its time efficiency.

The presented compression scheme is a novel solution that is based on deterministic vector clustering and encompasses three data reduction features in one on-chip decoding system. The approach preserves all benefits of continuous flow decompression and offers compression ratios of order 1000x with encoding efficiency much higher than 1.00.

The paper presents a BIST-based scheme for fault diagnosis that can be used to identify permanent and address independent failures in embedded read-only memories. The proposed approach offers a simple test flow and does not require intensive interactions between a BIST controller and a tester. The scheme rests on partitioning of rows and columns of the memory array by employing low cost test logic. It is designed to meet requirements of at-speed test thus enabling detection of time-related faults.

The paper presents a new scan chain selection scheme for response compaction. The proposed solution performs selective masking of scan chains and handles a wide range of unknown state profiles, such that all X states can be eliminated in a per-cycle mode while preserving high observability of scan cells that capture errors.

We will show the real implementation of a very high test compression scheme for a 3 pin image sensor device. This new approach results in achieving the same compression ratio of 27.7X and the same test coverage on 3 pins instead of 8 pins for a typical scan design.

The paper presents a BIST-based fault diagnosis scheme that can be used to identify a variety of failures in embedded memory arrays. The proposed solution employs flexible test logic to record test responses at the system speed with no interruptions of a BIST session. It offers a simple test flow and enables detection of time-related faults. Furthermore, the way the test responses are processed allows accurate reconstruction of error bitmaps.

This paper presents X-Press - a new two-stage test-response compactor that can be easily integrated with a multiple scan-chain environment. This compactor preserves all benefits of spatial compaction and offers, due to its overdrive sequential section, compression much higher than the ratio of scan chains to compactor outputs. X-Press is also capable of handling a wide range of unknown (X) state profiles by deploying a two-level scan-chain-selection mechanism. In addition to a new compactor architecture, original contributions of this paper include a detailed analysis of two-level error masking caused by X states and a new algorithm to both rank scan chains and then to determine, in per-pattern mode, scan-chain-selection rules used to suppress X states. Experimental results obtained for a variety of designs show feasibility and efficiency of the proposed compaction scheme, altogether with actual impact of X states on a test-pattern count. Finally, diagnostic capabilities of the proposed scheme accompanied by further experimental results are also analyzed.

In this paper, we propose a novel RTL testability analyzer based on logical virtual prototyping. A very fast synthesis engine is utilized to create a gate level hierarchical netlist with generic gates, which we call a logical virtual prototype, in this paper. Subsequently, ATPG and testability analysis are performed on the logical virtual prototype to provide RTL designers with a wealth of information that would allow them: (1) Accurately estimate / predict test coverage. (2) Generate patterns that can be used for gate-level design. (3) Identify hard-to-test design blocks in RTL, which can then be redesigned to improve coverage.

Field programmable memory BIST controllers are becoming a necessity to target manufacturing defects in embedded memories. For 65nm and below, random defects are not the only ones affecting the yield of a process. Systematic as well as parametric defects are now the predominant causes of memory failures and have to be addressed. Conventional memory BIST algorithms are usually targeted to catch random defects. In order to catch such systematic and parametric defects, it is necessary to have the flexibility to apply new algorithms to embedded memories after manufacturing. In this paper, a field programmable memory BIST architecture is proposed to support multiple loops within a test step of an algorithm, including nested loops. These controllers, therefore, guarantee supporting complex algorithm necessary to target defects during failure analysis that could help yield ramp up or reduce test escapes. In addition, the proposed architecture is modular in nature and allows optimizing the complexity of the controller along with area and performance

The paper presents a two-stage test response compactor with an overdrive section and scan chain selection logic. The proposed solution is capable of handling a wide range of X state profiles, offers compaction much higher than the ratio of scan chains to compactor outputs, and provides excellent diagnostic resolution

This paper presents an enhanced architecture of on-chip pseudorandom test pattern generators, test data decompressors, and test response compactors based on ring generators. The new structure is aimed at improving layout and routing properties while, at the same time, reducing propagation delays introduced by associated phase shifters.

Reduced pin count testing (RPCT) has proven to be an effective solution to reduce structural test costs in a manufacturing environment. Traditionally, RPCT has focused on stuck-at faults and IO loop-back tests. However, as circuit feature sizes shrink and new technology nodes employed, at-speed tests are becoming critical to assure low defect levels. In this paper, we extend the RPCT technique to allow application of atspeed test patterns using low cost testers that are seriously pin limited. Existing boundary scan cells are modified to facilitate the application of at-speed patterns thereby having minimal impact on the design and test area overhead.

In this talk, the EDT technology was introduced briefly along with a description of the hardware and the methodology used to achieve high test-data compression. The advantages of the approach in terms of encoding capacity, ability to handle unknowns, minimal hardware overhead, and close resemblance to a conventional ATPG flow were discussed. Since the technology requires very few pins to drive the decompressor from an ATE and observe responses at the output, it is attractive for burn-in test, core test, multisite testing, and is suitable for parts tested on VLCTs. The presentation touched upon these test techniques that directly benefit from using the proposed solution. With newer technology nodes, diagnosis is becoming critical for yield ramp up, faster time to volume, and first silicon debug. No compression solution is complete without an easy way to diagnose failures during manufacturing test. The ability to perform direct diagnosis from compressed patterns within the EDT framework were presented

A full-speed field-programmable memory BIST controller is proposed. The proposed instruction and architecture designs enable full-speed operation of not only March algorithms but also some non-linear algorithms that are becoming more and more important in modern memory testing, diagnosis, and failure analysis.

A design's increasing density, as well as its number of embedded memories increases its vulnerability to a variety of potential manufacturing defects. Standard March test algorithms used for obtaining good defect coverage must be augmented by new algorithms that target defects not screened by embedded BIST controllers. This paper presents our experience diagnosing address decode open faults (ADOF) using scan patterns. Subsequently, tests were added in the BIST controller to target ADOF. Other tests were added to screen potential bit/byte write-enable faults in memories with bit/byte write-enable controls

Nanometer technology have not only resulted in increasingly complex chips but is also exposing new defects and failure mechanisms during manufacturing that are challenging process and test engineers while they struggle to maintain high yield and low DPM. Silicon manufacturers are increasingly using structural test vectors to improve the process and consequently, reduce the defect rates. Structural vectors help detect defective parts and debug issues in an automated manner, which subsequently allows ramping up the yield for a given process fairly quickly. In addition, it reduces the number of escaped parts thereby guaranteeing lower DPM and fewer field returns. However, relying more on structural tests implies that the test set should be of the highest quality and may include vectors for fault models (in addition to stuck-at faults) such as transition, path-delay, bridging, n-detect, in-line resistance, Iddq, etc., covering some of the new failure mechanisms.

The paper presents enhanced architectures of pseudo-random test pattern generators and on-chip test data decompressors based on ring generators. The new structures are aimed at improving their layout and routing properties while at the same time reducing propagation delays introduced by associated phase shifters.

This paper presents a novel test-data volume-compression methodology called the embedded deterministic test (EDT), which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time. The presented scheme is widely applicable and easy to deploy because it is based on the standard scan/ATPG methodology and adopts a very simple flow. It is nonintrusive as it does not require any modifications to the core logic such as the insertion of test points or logic bounding unknown states. The EDT scheme consists of logic embedded on a chip and a new deterministic test-pattern generation technique. The main contributions of the paper are test-stimuli compression schemes that allow us to deliver test data to the on-chip continuous-flow decompressor. In particular, it can be done by repeating certain patterns at the rates, which are adjusted to the requirements of the test cubes. Experimental results show that for industrial circuits with test cubes with very low fill rates, ranging from 3% to 0.2%, these schemes result in compression ratios of 30 to 500 times. A comprehensive analysis of the encoding efficiency of the proposed compression schemes is also provided.

This paper presents a method to consider a given SOC with pin and peak power constraints, and simultaneously (1) determine an optimal wrapper width for each core, (2) allocate SOC pins to cores and (3) schedule core tests to minimize the test completion time. For the first time the stated problem is formulated as a restricted 3 dimensional bin-packing problem and a heuristic to determine an optimal solution is proposed.

This paper introduces embedded deterministic test (EDT) technology, which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time. The EDT architecture, the compression algorithm, design flow, experimental results, and silicon implementation are presented.

A method to solve the resource allocation and test scheduling problems together in order to achieve concurrent test for core-based system-on-chip (SOC) designs is presented in this paper. The primary objective for concurrent SOC test is to reduce test application time. The methodology used in this paper is not limited to any specific test access mechanism (TAM). Additionally, it can also be applied for test budgeting during the design phase to obtain a tradeoff between test application time and SOC pins needed. In this paper, the above problem is formulated as a well-known 2-dimensional bin-packing problem. A best fit heuristic algorithm is employed to obtain satisfactory results.

This paper presents a methodology to insert scan paths in a functional Register Transfer Level (RTL) specification of a design that can exploit existing functional paths between sequential elements in the original circuit for establishing scan chains. The primary objective for RTL scan insertion is to reduce the time taken for DFT, and thus reduce the time to market. Additionally, building scan chains at the functional RT-Level is expected to reduce the total area overhead introduced by full scan without compromising the fault coverage achieved. In addition, it often eliminates the delay associated with the additional multiplexer as a part of a conventional scan-cell in high performance designs. Experimental results presented in this paper demonstrate that the proposed method achieves the above objectives while also achieving higher fault coverages for most of the benchmark circuits considered.

This paper presents a new pseudoexhaustive test methodology for digital finite impulse response (FIR) filters. The proposed scheme can be employed to detect any combinational faults within the basic cell of the functional units occurring in linear phase comb filters, trees of sign-extended adders and phase-shift multipliers. It uses additive generators as a source of pseudoexhaustive patterns to systematically test all FIR filter building blocks.

Path-delay faults represent a fault model that is commonly used to detect timing anomalies in a circuit. Unlike stuck-at faults which can be detected using ATE at lower speed, test for path-delay faults require ATEs that can run at the clock frequency of the circuit under-test. However, with ever-increasing circuit-speed and complexity, ATEs are unable to keep up with this growing trend. Moreover running deterministic tests for timing related defects on expensive ATEs for high-speed circuits consume enormous test application time. In this paper, we propose a BIST methodology for path-delay faults in sequential circuits. The proposed technique is based on an existing BIST architecture for stuck-at faults such that timing faults in a circuit can also be addressed with minimum additional effort. A new clocking scheme along with a novel technique for placing observation points that increases the fault coverage for path-delay faults is presented. Experimental results on some benchmark circuits show high path-delay fault coverage for sequential circuits.

This paper presents a new pseudo-exhaustive test methodology for digital finite impulse response (FIR) filters. The proposed scheme can be employed in a built-in self-test (BIST) environment to detect any combinational faults occurring in linear phase comb filters, trees of sign-extended adders and phase-shift multipliers. It uses additive generators as a source of pseudo-exhaustive patterns to test systematically all FIR filter building blocks.

The usage of multipliers in fixed-width data-dominated architectures (also termed data paths) poses serious testability problems. Due to truncation of their outputs, the fault observability of the multipliers degrades, and the resulting output patterns are inadequate to completely test functional blocks that are driven by them. Consequently, the overall random pattern testability of data paths deteriorates substantially. In this paper, we propose new generic design schemes, based on residue number system arithmetic, to improve the overall testability of data paths. The approach uses, in the test mode, the truncated least significant bits of the product to increase the variety of patterns at the output of a multiplier. This, in turn, improves the fault detectability of multipliers, and consequently, have a remarkable impact on the overall testability of data paths. The proposed techniques can be incorporated with a minimal performance degradation and area overhead, and are independent of the multiplier architecture. Experimental analysis performed on four high-level synthesis benchmarks exhibits a significant improvement in the overall testability of the corresponding data-path implementations.

This paper demonstrates how fault simulation of building blocks found in data-path architectures can be performed extremely efficiently and accurately by taking advantage of their simple functional models and structural regularity.This technique can be used to accelerate the simulation of those blocks in virtually any fault simulation environment, resulting in fault simulation algorithms that can perform fault grading in a very demanding BIST environment.

The usage of multipliers in the increasingly demanding fixed-width data path architectures poses serious testability problems. Their truncated outputs not only degrade the fault observability, but the output responses of multipliers are inadequate to completely test functional blocks that are driven by them. In this paper, we propose a new design for testability scheme to improve the overall testability of data paths. The methodology takes into account the truncated least significant bits of the product in the test mode to increase the variety of patterns at the output of a multiplier. The proposed techniques are part of the Arithmetic Built-in Self Test methodology and can be incorporated with a minimal performance degradation and area overhead.

In this paper, we propose an entirely new Built-in Self Test scheme for high-level synthesis of data path architectures that makes use of the arithmetic blocks in the data path to generate test vectors and compact test responses. The paper employs state coverage to evaluate testability in an abstract level, and subsequently, use it to guide the synthesis of testable circuits.