Demo Data from EDBT 2026 / reviewers in the wild / expert
Jinsuo Zhang
dblp:16/5410
· DBLP profile ↗
3ranked-venue papers
1as first author
0since 2021 · last 2006
0000-0002-3412-7769ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1Software engineering, systems software and programming languages · 1 · 1 first-authorApplied, interdisciplinary, general and emerging computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 65% Processor architecture and microarchitecture · 35% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems
cache |
0.0 | 1 | 2001 | Direct load: dependence-linked dataflow resolution of load address and cache coordinate · MICRO 2001 |
Memory systems › memory access latency
cache access latency |
0.0 | 1 | 2001 | Direct load: dependence-linked dataflow resolution of load address and cache coordinate · MICRO 2001 |
Memory systems › memory access latency
load latency |
0.0 | 1 | 2001 | Direct load: dependence-linked dataflow resolution of load address and cache coordinate · MICRO 2001 |
Processor architecture and microarchitecture
out-of-order execution |
0.0 | 1 | 2001 | Direct load: dependence-linked dataflow resolution of load address and cache coordinate · MICRO 2001 |
Processor architecture and microarchitecture
instruction-level parallelism |
0.0 | 1 | 2001 | Direct load: dependence-linked dataflow resolution of load address and cache coordinate · MICRO 2001 |
Processor architecture and microarchitecture › special-purpose processor › application-specific processor design
instruction path coprocessor |
0.0 | 1 | 2001 | Direct load: dependence-linked dataflow resolution of load address and cache coordinate · MICRO 2001 |
Methods — techniques the papers use, named apart from their topics
stride-based prediction · 0.0simplescalar · 0.0dependence-linked dataflow · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2006 | UbiNet: A Generic and Ubiquitous Service Provider FrameworkabstractIn mobile environment, it is very common that mobile devices periodically stay in disconnection mode. In a networked world as today, computer users rely on network services so heavily that even a short duration of disconnection from network will dramatically distract user's normal activity. Past researches explored disconnected operation for file system and database access. In this paper, we introduce and evaluate a ubiquitous network service framework. The proposed framework combines the advantages of both disconnection operation and system virtualization in order to provide 7/24 services to mobile users. We implemented and validated our idea in both Linux and Windows platform. From our initial deployment and daily usage experiment, our architecture is highly feasible and deployable. In this paper, we will illustrate the architecture, implementation, and performance evaluation based on our implemented system. Jinsuo Zhang, Abdelsalam Helal |
ICSEA | 1 |
| 2001 | A Three-Tier Architecture for Ubiquitous Data AccessabstractWe present a three-tier architecture of middleware that addresses challenges facing accessibility, availability, and consistency of data in mobile environments. The architecture supports the automatic hoarding of data from multiple, heterogeneous sources into possibly a variety of different mobile devices. The middle tier enables the automation of synchronization tasks in both connected mode (following disconnection) and weakly connected mode, where only intelligent and effective synchronization can be used in the presence of a low-bandwidth network. We present the three-tier architecture based on the Coda file system. Abdelsalam Helal, Joachim Hammer, Jinsuo Zhang, Abhinav Khushraj |
AICCSA | 3 |
| 2001 | Direct load: dependence-linked dataflow resolution of load address and cache coordinateabstractAn increasing cache latency in future processors incurs profound performance impacts in spite of advanced out-of-order execution techniques. In this paper, we describe an early address resolution mechanism that accurately resolves both regular and irregular load addresses. The basic idea is to build dynamic dependence links from the instruction that updates the base register to the consumer load instructions. Once a new base address is available, it triggers calculations of the new load addresses for dependent loads. Furthermore, the exact cache location of the requested data is predicted based on the newly resolved load address. As a result, this direct load can access the data cache directly to achieve a zero-cycle load latency. Performance evaluation using SPEC integer programs shows that the dynamic dependence links can be established accurately. Combined with a stride-based predictor, the proposed early address resolution achieves about 97% average accuracy with less than 1% misprediction. Based on a modified SimpleScalar model, the proposed method can potentially improve the IPC by about 18%. Byung-Kwon Chung, Jinsuo Zhang, Jih-Kwon Peir, Shih-Chang Lai, Konrad Lai |
MICRO | 2 |