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Emanuele Giaquinta

dblp:16/5567 · DBLP profile ↗
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16ranked-venue papers
6as first author
0since 2021 · last 2019
0000-0002-9473-3971ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Theory of computation · 10 · 5 first-authorDatabases, data management, data science and information retrieval · 7 · 2 first-authorSystems, architecture and hardware · 2 · 1 first-authorSoftware engineering, systems software and programming languages · 1Graphics, computer vision, multimedia, augmented reality and games · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 73% Hardware accelerators and domain-specific architectures · 23% Processor architecture and microarchitecture · 4%
Theoretical computer science
1 paper
Automata and formal languages · 67% Algorithms and data structures · 33%

Topics — the 7 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
high-level synthesis
0.622019
RegionSeeker: Automatically Identifying and Selecting Accelerators From Application Source Code · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2019
Maximum Convex Subgraphs Under I/O Constraint for Automatic Identification of Custom Instructions · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2015
Electronic design automation › high-level synthesis
accelerator synthesis
0.412019
RegionSeeker: Automatically Identifying and Selecting Accelerators From Application Source Code · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2019
Electronic design automation › hardware/software co-design
custom instruction identification
0.212015
Maximum Convex Subgraphs Under I/O Constraint for Automatic Identification of Custom Instructions · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2015
Automata and formal languages
finite automata
0.112012
A compact representation of nondeterministic (suffix) automata for the bit-parallel approach · Inf. Comput. 2012
Automata and formal languages › finite automata › nondeterministic finite automata
nondeterministic automata
0.112012
A compact representation of nondeterministic (suffix) automata for the bit-parallel approach · Inf. Comput. 2012
Algorithms and data structures › sequence algorithms
string algorithms
0.112012
A compact representation of nondeterministic (suffix) automata for the bit-parallel approach · Inf. Comput. 2012
Processor architecture and microarchitecture › instruction set architecture
instruction set extension
0.112015
Maximum Convex Subgraphs Under I/O Constraint for Automatic Identification of Custom Instructions · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2015

Methods — techniques the papers use, named apart from their topics

control flow graph analysis · 0.4LLVM · 0.4graph enumeration · 0.2convexity analysis · 0.2
YearPublicationVenuePosition
2019 RegionSeeker: Automatically Identifying and Selecting Accelerators From Application Source Code
abstract
Embedded systems present stringent and often conflicting requirements. On the one side, the need for high performance within a tight energy budget favors inflexible Application Specific Integrated Circuit (ASIC) implementations; on the other side, a short time-to-market demands programmability. Hybrid architectures such as special-purpose customized processors represent an attractive solution, as they are programmable by software, but use dedicated hardware to accelerate parts of the computation. In such a scenario, the capability of automatically identifying the computation parts to be realized in hardware is highly desirable, in order to reduce design time and effort. This paper aims at advancing the state-of-the-art in this field. We recognize that subgraphs of control flow graphs having a single input control point and a single output control point, that we call regions, are good targets for the synthesis of application specific hardware accelerators. We therefore provide a method to identify them and an LLVM-based toolchain (named RegionSeeker) that, analyzing a software application, automatically selects its most profitable regions given an area constraint. Experimental evidence shows that the accelerators identified by RegionSeeker provide a speedup of up to $4.6\boldsymbol {\times }$ and, on average, approximately 30% higher speedup is achieved compared to state-of-the-art identification techniques.
Georgios Zacharopoulos 0001, Lorenzo Ferretti, Emanuele Giaquinta, Giovanni Ansaloni, Laura Pozzi 0001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3
2017 Technology beats algorithms (in exact string matching)
abstract
Summary More than 120 algorithms have been developed for exact string matching within the last 40 years. We show by experiments that the naïve algorithm exploiting SIMD instructions of modern CPUs (with symbols compared in a special order) is the fastest one for patterns of length up to about 50 symbols and extremely good for longer patterns and small alphabets. The algorithm compares 16 or 32 characters in parallel by applying SSE2 or AVX2 instructions, respectively. Moreover, it uses loop peeling to further speed up the searching phase. We tried several orders for comparisons of pattern symbols, and the increasing order of their probabilities in the text was the best.
Jorma Tarhio, Jan Holub 0001, Emanuele Giaquinta
Softw. Pract. Exp.3
2015 Filtration Algorithms for Approximate Order-Preserving Matching
Tamanna Chhabra, Emanuele Giaquinta, Jorma Tarhio
SPIRE2
2015 Run-Length Encoded Nondeterministic KMP and Suffix Automata
Emanuele Giaquinta
CIAA1
2015 Longest common substrings with k mismatches
abstract
The longest common substring with k-mismatches problem is to find, given two strings S1 and S2, a longest substring A1 of S1 and A2 of S2 such that the Hamming distance between A1 and A2 is ≤k. We introduce a practical O(nm) time and O(1) space solution for this problem, where n and m are the lengths of S1 and S2, respectively. This algorithm can also be used to compute the matching statistics with k-mismatches of S1 and S2 in O(nm) time and O(m) space. Moreover, we also present a theoretical solution for the k=1 case which runs in O(nlog⁡m) time, assuming m≤n, and uses O(m) space, improving over the existing O(nm) time and O(m) space bound of Babenko and Starikovskaya [1].
Tomás Flouri, Emanuele Giaquinta, Kassian Kobert, Esko Ukkonen
Inf. Process. Lett.2
2015 Maximum Convex Subgraphs Under I/O Constraint for Automatic Identification of Custom Instructions
abstract
Automatic identification of custom instructions (CI) is the process of supporting the programmer in choosing automatically beneficial parts of the application source code that can then be synthesized and run on dedicated hardware. Identification is typically modeled as choosing a subgraph from a graph, representing the application, that has the highest speedup potential when implemented in custom hardware, and that fulfills the constraints of convexity and of a given maximum number of inputs and outputs. Existing algorithms for CI identification either enumerate all the valid subgraphs under the constraints of convexity and I/O, or return the subset of all maximal valid subgraphs with respect to convexity only. The downside of the former approach is that enumerating all valid subgraphs is costly, especially for large values of input and output constraints, while we may be interested in the subgraphs which obtain the best speedup only. Instead, the latter approach may fail to find a feasible solution, since the valid subgraphs with respect to convexity only can be too large to be useful. In this paper, we present a novel approach which attempts to fill the gap between the existing methods. In particular, we present an algorithm that enumerates the subset of all maximum valid subgraphs with respect to convexity and number of inputs and outputs. Our method revisits and combines the existing approaches and yields an algorithm which is effective and outperforms the state-of-the-art for large values of input and output constraints.
Emanuele Giaquinta, Anadi Mishra, Laura Pozzi 0001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
2014 Text searching allowing for inversions and translocations of factors
Domenico Cantone, Simone Faro, Emanuele Giaquinta
Discret. Appl. Math.3
2014 On a compact encoding of the swap automaton
Kimmo Fredriksson, Emanuele Giaquinta
Inf. Process. Lett.2
2014 Motif matching using gapped patterns
Emanuele Giaquinta, Kimmo Fredriksson, Szymon Grabowski, Alexandru I. Tomescu, Esko Ukkonen
Theor. Comput. Sci.1
2013 Motif Matching Using Gapped Patterns
Emanuele Giaquinta, Kimmo Fredriksson, Szymon Grabowski, Esko Ukkonen
IWOCA1
2013 Indexes for Jumbled Pattern Matching in Strings, Trees and Graphs
Ferdinando Cicalese, Travis Gagie, Emanuele Giaquinta, Eduardo Sany Laber, Zsuzsanna Lipták, Romeo Rizzi, Alexandru I. Tomescu
SPIRE3
2013 New algorithms for binary jumbled pattern matching
Emanuele Giaquinta, Szymon Grabowski
Inf. Process. Lett.1
2013 Approximate pattern matching with k-mismatches in packed text
Emanuele Giaquinta, Szymon Grabowski, Kimmo Fredriksson
Inf. Process. Lett.1
2012 A compact representation of nondeterministic (suffix) automata for the bit-parallel approach
Domenico Cantone, Simone Faro, Emanuele Giaquinta
Inf. Comput.3
2011 String matching with inversions and translocations in linear average time (most of the time)
Szymon Grabowski, Simone Faro, Emanuele Giaquinta
Inf. Process. Lett.3
2010 A Compact Representation of Nondeterministic (Suffix) Automata for the Bit-Parallel Approach
Domenico Cantone, Simone Faro, Emanuele Giaquinta
CPM3