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Engel Roza

dblp:16/5592 · DBLP profile ↗
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5ranked-venue papers
4as first author
0since 2021 · last 2007
0000-0002-4911-9948ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 4 · 4 first-authorSystems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer networks
4 papers
Physical-layer communications · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 100%

Topics — the 9 heaviest of 9, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Physical-layer communications › equalization
decision feedback equalization
0.021979
A Novel Concept for a Hybrid 140 Mbit/s System · IEEE Trans. Commun. 1979
A Practical Design Approach to Decision Feedback Receivers with Conventional Filters · IEEE Trans. Commun. 1978
Physical-layer communications
equalization
0.021979
A Novel Concept for a Hybrid 140 Mbit/s System · IEEE Trans. Commun. 1979
A Practical Design Approach to Decision Feedback Receivers with Conventional Filters · IEEE Trans. Commun. 1978
Physical-layer communications
digital transmission systems
0.011979
A Novel Concept for a Hybrid 140 Mbit/s System · IEEE Trans. Commun. 1979
Physical-layer communications
receiver design
0.011978
A Practical Design Approach to Decision Feedback Receivers with Conventional Filters · IEEE Trans. Commun. 1978
Physical-layer communications › relaying › relay systems
regenerative repeaters
0.011977
An Experimental 560 Mbits/s Repeater with Integrated Circuits · IEEE Trans. Commun. 1977
Integrated circuit design
high-speed integrated circuits
0.011977
An Experimental 560 Mbits/s Repeater with Integrated Circuits · IEEE Trans. Commun. 1977
Physical-layer communications › modulation › pulse modulation
PCM transmission
0.011974
Analysis of Phase-Locked Timing Extraction Circuits for Pulse Code Transmission · IEEE Trans. Commun. 1974
Physical-layer communications › synchronization
timing recovery
0.011974
Analysis of Phase-Locked Timing Extraction Circuits for Pulse Code Transmission · IEEE Trans. Commun. 1974
Physical-layer communications › digital transmission systems › wireline communication
coaxial cable transmission
0.011977
An Experimental 560 Mbits/s Repeater with Integrated Circuits · IEEE Trans. Commun. 1977

Methods — techniques the papers use, named apart from their topics

monolithic integration · 0.0tolerance analysis · 0.0polynomial design · 0.0phase error analysis · 0.0laguerre polynomials · 0.0jitter propagation analysis · 0.0
YearPublicationVenuePosition
2007 Design of MOS transconductors with low noise and low harmonic distortion for minimum current consumption
Sotir Ouzounov, Engel Roza, Hans Hegt, Gerard van der Weide, Arthur H. M. van Roermund
Integr.2
1979 A Novel Concept for a Hybrid 140 Mbit/s System
abstract
In this paper it is shown that non-linear equalization by decision feedback offers such a large advantage in signal-to-noise ratio and bandwidth economy that a hybrid binary 140 Mbit/s system is possible with compatibility in repeater spacing in existing European ternary regenerative systems. A large number (60) of analog sections can be connected in tandem. Hardware models of analog and digital sections are described and a detailed analysiS of tolerances is given.
Engel Roza, Jan G. M. van Thuyl, Willem van Doorn
IEEE Trans. Commun.1
1978 A Practical Design Approach to Decision Feedback Receivers with Conventional Filters
abstract
A method for designing conventional filters for decision feedback systems is described. Practical considerations, such as error propagation effect, timing inaccuracy and complexity, are incorporated in the design rules. In particular, non-band-limited noisy transmission channels and channels impaired by bandwidth limitation are investigated. In addition, noise and bandwidth limitations are taken into account simultaneously. The design approach is based upon polynomial descriptions which reveal simple relationships between the forward and feedback path, a stability measure which is representative of the error propagation, and an evaluation in terms of Laguerre polynomials. Results of simulations in hardware are given by way of a practical example and a binary regenerative transmission system for coaxial cables is studied.
Engel Roza
IEEE Trans. Commun.1
1977 An Experimental 560 Mbits/s Repeater with Integrated Circuits
abstract
The bandwidth penalty of digital systems is very obvious in the case of transmission over coaxial cables because of the exponential increse of cable attenuation with square root of frequency. From capacity point of view, it is only at very high information rates (> 500 Mbit/s typically) that a digital system might be competitive with an analog system, because the disadvantage of noise accumulation in an analog system ultimately cancels the bandwidth penalty of the digital system. In addition, it is, however, difficult to realize common functions, such as amplification, equalization, regeneration, clock extraction, etc. with electronic components having a frequency range comparable to the frequency range of the information signal, which extends from zero frequency to the microwave range. Besides, the complexity of a regenerative repeater should be kept to a minimum for reliability reasons. It is shown in the paper that with present-day technology a 560 Mbit/s repeater can be constructed, operating in sections of 1.5 km coaxial cable (2.6/9.5 mm). Also, we demonstrate that new technologies exist which may lead to repeaters with a high degree of monolithic integration, even at such a speed, which is important from the reliability viewpoint. The constructed and described repeater is characterized by unconventional and economic design of amplifier/equalizer and clock extractor and by monolithically integrated decision circuits.
Engel Roza, Peter W. Millenaar
IEEE Trans. Commun.1
1974 Analysis of Phase-Locked Timing Extraction Circuits for Pulse Code Transmission
abstract
An analysis is presented of the performance of phaselocked timing extraction circuits for baseband pulse code transmission. The phase error of the extracted timing wave is influenced by the properties of three essential stages in signal processing: prefiltering, nonlinear treatment, and narrow-band filtering. The analysis enables us to calculate quantitatively the quasi-static and the dynamic part of the phase error for arbitrary but specified types of signal processing. This is more than can be done with existing theory in the case of resonant-type timing extraction circuits. Examples are given for practical cases, and conditions for optimum performance are derived. Furthermore, the behavior of such phase-locked circuits in a chain of repeaters is investigated, and in particular, the propagation law for jitter. Byrne's model, as used for resonant-type timing extraction circuits, therefore is generalized. It is shown analytically and experimentally that by proper implementation of the timing extraction circuit, considerable improvement can be obtained as compared with resonant-type circuits.
Engel Roza
IEEE Trans. Commun.1