Modern digital systems require one or more frequency shaping modules that realize certain transfer functions, usually in the form of digital filters. Breaking up the design into multiple stages results in reducing the implementation area and power consumption. However, there is no well-defined automation methodology to design an optimum multistage multirate filter. This article proposes a new design flow automation tool using a hybrid sampling strategy-based differential evolution (HSS-DE). The user specifies the inputs and outputs of the system, including the input spectrum, the sample rate change, the magnitude and phase responses, and the required signal-to-noise ratio. The tool uses this information to generate a solution indicating the number of stages and the filters' specifications for each stage such that the generated architecture satisfies the user requirements. We compared the proposed tool to subsystems designed by experts in the ASIC industry. Several case studies are presented to demonstrate the proposed tool's efficiency in different design problems. The case studies include decimation filters for sigma-delta (ΣΔ) analog-to-digital converters (ADCs) and interpolation filters for wideband transmitters such as wideband code division multiple access (WCDMA). The case studies' results indicate that the proposed design automation flow reduces the design time remarkably, in addition to reducing the implementation in all cases.

In this paper, we present an IoT application targeting food quality. We utilize the spectrometer as a ubiquitous sensor to provide a Near-infrared (NIR) spectrum that can be used to develop regression models targeting milk quality. We solve a regression problem for different milk components such as Fat, Protein, Lactose, and Solids-Non-Fat. We apply a variety of comparative configurations of regression models, pre-processing techniques, wavelength selection, and feature extraction methods. Our study shows that for the milk data, non-linear models (GPR and SVR) are better choices when compared to linear models.

Typical modern HW designs include many blocks associated with thousands of design properties. Having today's commercial formal verifiers utilize a complementary set of state-of-art formal algorithms is a key in enabling the formal verification tools to successfully cope with verification problems of different sizes, types, and complexities. Formal engines orchestration is the methodology used to pick the most appropriate formal engine for a specific verification problem. It assures proper scheduling of the formal engines to minimize the time consumed to solve individual design verification problems, hence highly impacts the time required to verify the overall design properties. This work proposes the utilization of supervised machine learning classification techniques to guide the orchestration step by predicting the formal engines that should be assigned to a design property. Up to 16,500 formal verification runs on RTL designs and their properties are used to train the classifier to create a prediction model. The classifier assigns any new verification problem to an appropriate list of formal engines associated with a probability distribution over the set of engines classes. Our results indicate how the proposed model is able to improve the formal suite total run-time by up to 59% of its maximum allowable time improvement using multi-classification-based orchestration and to nominate with 88% accuracy the appropriate formal engines for new-to-verify HW designs.

Modern graphical processing units (GPUs) are equipped with general-purpose L1 and L2 caches to reduce the memory bandwidth demand and improve the performance of some irregular general-purpose GPU (GPGPU) applications. However, due to the massive multithreading, GPGPU caches suffer from severe resource contention and low data-sharing which may lead to performance degradation instead. This paper proposes a low-cost streaming-aware conflict-avoiding thrashing-resistant (SACAT) GPGPU cache management scheme that efficiently utilizes the GPGPU cache resources and addresses all the problems associated with GPGPU caches. The proposed scheme employs three orthogonal techniques. First, it dynamically detects and bypasses streaming applications at fine granularity. Second, a dynamic warp throttling via cores sampling (DWT-CS) is proposed to alleviate cache thrashing. DWT-CS runs an exhaustive search over cores to find the best number of warps that achieves the highest performance. Third, it employs pseudo random interleaving cache (PRIC), which is an improved cache indexing function based on polynomial modulus mapping, to mitigate associativity stalls and eliminate conflict misses. Experimental results demonstrate that the proposed scheme achieves a 1.87× and a 1.5× performance improvement over the cache-conscious wavefront scheduler (CCWS) and the memory request prioritization buffer (MRPB), respectively.

This paper proposes a framework to automatically generate functional coverage model for the Design under Verification (DUV). The coverage goals are identified to cover different combinations of the design inputs, outputs, Finite State Machines (FSMs) valid states/transitions and internal signals that control the guard expressions of the design control flow. Additionally the cross coverage of highly correlated design variables is added to the final coverage model and generated using data mining techniques. The proposed framework illustrates how formal methods can be used to automate the identification of unreachable coverage-points and then automatically generate the exclusion of those coverage items for final accurate coverage results calculations. Formal verification is also utilized to generate test scenarios (counter examples) for reachable coverage goals that have not been covered in initial random simulation runs. Our experimental results demonstrate the effectiveness of the proposed approach in closing the coverage loop for a set of today's RTL designs.

Double patterning lithography (DPL) is seen as one of the most promising solutions for new technology nodes such as 32nm and 22nm. However, DPL faces the challenges of handling layout decomposition and overlay errors. Currently, most DPL solutions use post-layout decomposition which requires multiple iterations and designer intervention to achieve a decomposable layout as designs scale larger. Recent research is starting to consider DPL constraints during the layout design phase especially during the detailed routing phase. In this work, we propose DPL-aware grid-based detailed routing algorithm supported with online conflict resolution. The conflict resolution algorithm uses a graph structure to represent geometrical relations between routed polygons and helps in conflict detection and color assignment. Experimental results indicate that this enhanced algorithm reduces the number of conflicts by 60% on average.

This paper studies the problem of automatic assertion extraction from simulation traces. Previous approaches to the assertion generation problem have focused on a single aspect of automatic assertion extractions, and have yielded often unfavorable results. We propose a framework that combines searching for known assertion via templates with frequent and sequential patterns mining, while constraining the search by some knowledge about the design. These constraints can be automatically extracted using static analysis methods from the Register Transfer Level (RTL) description of the design, or as a user input to the assertion detector. Our experimental results show that this approach helps in the detection of assertion patterns that are typically common and widely used in today's RTL designs.

Cell search has to be performed by the user equipment in 3GPP Long Term Evolution (LTE) systems to obtain cell identity before connecting to the cell. The cell identity is transmitted using the Primary Synchronization Symbol (PSS) and the Secondary Synchronization Symbol (SSS). The PSS carries one of three possible values for the sector identity whereas the SSS carries one of 168 possible values for the physical cell identity. Straightforward implementation of SSS detection incurs a large area due to the large number of required correlators. This paper presents a complete design and hardware implementation for the detection of the SSS. The fixed point representation of the proposed system design is optimized to use the smallest word lengths at various system nodes while maintaining the overall performance within acceptable limits. Different architectures are studied, compared and an all-serial architecture is chosen to minimize the design area and power consumption, while achieving an acceptable acquisition time.

System-level design of packet switching fabrics focuses on performance metrics and rarely considers the physical requirements that are usually addressed later at the circuit-level. However, low-power dissipation has become a major requirement in such fabrics dictated by the requirements of emerging applications and by the recent advances in fabrication and VLSI technologies. This paper proposes a framework for system-level design of packet switching fabrics that integrates performance specifications along with physical requirements and constraints. Moreover, realistic traffic models are used to derive the transition activity and the packet arrival and departure events needed for power estimation. Physical requirements are defined by an architectural model for power dissipation based on the stochastic traffic model, models for silicon area, chip count, and input-output pins, which provide a complete system-level specification of the fabric. Performance constraints are also derived from the stochastic traffic model. This framework formulates and solves the power optimization problem subject to those physical and performance constraints as an integer nonlinear optimization problem. The results obtained emphasize the importance of traffic-driven system-level optimization and show the efficiency of this framework as a system-level design space exploration tool.

With the explosive growth of electronic commerce, dedicated cryptographic processors are becoming essential since general-purpose processors cannot provide the performance and functionality directly needed, This paper proposes an architecture for a versatile Galois field GF(2/sup m/) processor for cryptographic applications. This processor uses both canonical and triangular bases for field elements representation and manipulation. The variable dimension datapath of the processor is versatile enough to meet the varying requirements for different applications and environments. To provide flexibility for different cryptographic applications, an instruction set architecture is designed. Finally, a prototype VLSI implementation of the Galois field processor is presented and discussed.

In this paper a VLSI architecture is proposed for an algorithm-agile encryptor for ATM networks. The architecture is based on a circular sorting queue that buffers and switches incoming cells to the appropriate encryption pipelines. It also handles multicast cells that require different encryption algorithms for different destinations. Delay and loss priority are analyzed for multi-class traffic processed through the encryptor. The analysis results are necessary to size the buffer properly and to choose an appropriate priority scheme. An ASIC prototype of the sorting queue that supports an aggregate traffic rate of up to 21.2 Gbps is also presented.

Unlike most research involving finite field multipliers, this work targets a low-power multiplier through the application of various power reduction techniques to different types of multipliers and comparing their power consumption among other factors, rather than comparing complexity measures such as gate count or area. Gate count is used as a starting point to choose potential architectures, namely, polynomial and normal basis architectures. Power reduction techniques employed are mainly concerned with architecture- and logic-level low-power techniques. They include supply voltage reduction, power cost estimations, using low-power logic families and pipelining.