A new class of CMOS VLSI asynchronous sequential circuits utilizing pass transistors is introduced. This class of self synchronizing circuits eliminates the need for critical race free state assignments. These circuits synchronize the transition path action by forcing the circuit to sequence through proper unstable states.>

The authors report a novel design technique to reduce output switching noise in CMOS VLSI circuits. The technique is based on analysis of the RLC equivalent circuit of the output driver stage. SPICE simulations verify the method's effectiveness and a test circuit is being submitted to MOSIS for fabrication.>

Design techniques to make CMOS logic circuits fail-safe are reported. The set of transistor stuck-on and stuck-open faults, signal lines stuck-at faults, and bridging faults is partitioned into two classes of faults. Fail-safe property is maintained for multiple faults within a class. Limited fault tolerance capability is introduced as a by-product.>

A CAD tool for automatic generation of VLSI state machines based on a sequence invariant architecture is presented. The program, which is process independent, operates on a flow table input and produces a layout archive. Using an incremental approach for layout also allows subcircuits to be generated.>

A full custom, 25 MHz, 1.6 mu m CMOS correlator chip is presented. The 5.15 mm by 4.23 mm chip performs either autocorrelation or crosscorrelation, consuming less than 10 mW per channel. The correlator, designed for a space borne spectrometer, contains 32 channels and is cascadable. The correlator was designed to Mil Spec, 3 sigma Worst Case Speed parameters.>

Minimal test sets have the property that each input test vector tests simultaneously several faults in a circuit. Existing techniques use Boolean simplification or Karnaugh maps to achieve minimization. The authors present two new methods, one of which is a simple design by inspection technique and the other is a graphical technique. The process of minimization has been simplified by adopting the unique approach of first finding all the faults that can be detected by a single test.>

A VLSI implementation of a Reed-Solomon codec circuit is reported. The 1.6- mu m double metal CMOS chip is 8.2 mm by 8.4 mm, contains 200000 transistors, operates at a sustained data rate of 80 Mbits/s and executes up to 1000 MOPS while consuming less than 500 mW of power. The 10-MHz sustained byte rate for the data is independent of the error pattern. The circuit has complete decoder and encoder functions and uses a single data/system clock. Block lengths of 255 bytes as well as shortened codes are supported with no external buffering. Erasure corrections as well as random error corrections are supported with selectable correction of up to ten symbol errors. Corrected data is output at a fixed latency. These features make this Reed-Solomon processor suitable for use in advanced television systems.>