This paper proposes the first simultaneous wireless power and data transfer (SWPDT) integrated circuit (IC) which exploits a Capacitive-Inductive Channel (CI-Channel), enabling concurrent power and data transmission. The communication across the CI-Channel can support data-only transmission or can be incorporated into the system control loop, allowing output voltage regulation through phase-shift control applied at the primary side. The proposed IC can be configured as primary side (power transmitter, P-TX, and data receiver, RX) or secondary side (power receiver, P-RX, and data transmitter, TX). In order to ensure communication robustness, unwanted disturbances are removed through specifically designed Power Blanking and Ringing Blanking circuits. The proposed SWPDT IC test-chip prototype was fabricated using a 130-nm BCD process and experimentally verified considering the complete wireless power transfer (WPT) system, including primary side, CI-Channel and secondary side. The overall system, targeting medium-power industrial applications, achieves a maximum 5.3-W output power, a peak efficiency of 83.7% and a load regulation of 0.09 mV/mA. Moreover, a 540 kb/s data rate with no transmission errors across$10^{9}$bit acquisitions, corresponding to a bit-error-rate (BER)$\lt 10^{-9}$, was achieved.

This paper focuses on control techniques for an integrated Dual Active Bridge (DAB) converter designed for low-voltage (5V) and low-power (2W) applications. The analysis concentrates on the single-phase-shift (SPS) modulation, as it offers the best balance between implementation simplicity and power efficiency for a control loop circuit that must be embedded within the system. Moreover, an innovative modulation technique called controlled single-phase-shift (CSPS) is introduced, which dynamically adjusts the phase-shift to maximize current flow through the load. This approach enhances the output power range by 33%, achieving an increase in the average efficiency throughout the phase-shift interval up to 4% when compared to the conventional SPS modulation. Circuit-level simulations have been conducted in Cadence Virtuoso environment to verify the effectiveness of the proposed approach.

This paper presents a novel capacitive-inductive structure implementing the channel for power and data transmission in a wireless power transfer system. The structure consists of two$24-\mu\mathrm{H}$coil inductors, each surrounded with an open ring copper layer realized on a printed circuit board (PCB). The proposed channel structure allows simultaneous transmission of power and data: indeed power is transferred through the magnetic field generated by the coils, while data are modulated and transferred through the electric field produced by the capacitance determined by the copper rings and the parasitic capacitance of the two coils. The proposed structure was extensively studied and characterized both through simulations and measurements: compared to the state-of-the-art, in which metal plates placed below the coils are employed for implementing the capacitance used for data transmission, it shows a significant decrease in parasitic capacitance between the copper ring and the coil, thus reducing power disturbances on the data transmission.

Resonant power converters represent a step further in the effort of increasing the operating frequency, and consequently the power density, with respect to conventional switching converter architectures. Nevertheless, resonant converters are used only in very specific applications. The main issue is their design that, being not based on a solid mathematical background, results in a non-trivial task. In this paper we present a prototype of a class-E resonant converter with a simplified architecture, allowing both a small size (and so a higher density) and a simple mathematical analysis. Conversely with respect to the state-of-the-art approach, the circuit design is obtained by means of a semi-analytic mathematical approach without any support from circuital simulation. Measurements confirm the performance expected according to the mathematical model, and prove that the design of circuits with the proposed architecture can be effectively achieved with the developed mathematical model.

This paper presents a new approach for the design of a class-E resonant dc-dc converter. The small number of passive components featured by the considered topology allows to exactly solve the differential equations regulating the circuit evolution, and to develop a semi-analytic design procedure based on the differential equations solution. This represents an important breakthrough with respect to the state-of-the-art, where class-E circuit analysis is always based on strong simplifying assumptions, and the exact circuit design is achieved by means of numerical simulations after many time-consuming parametric sweeps.

Though compressive sensing hinges on extracting linear measurements from the signals to acquire, actual implementations introduce nonlinearities whose effect can be far from negligible. We here address the problem of saturation in the circuit blocks needed by a Random Modulation Pre-Integration architecture. To allow a fair a comparison with previous analysis, we rely on a model capturing the essentials of saturations in actual implementations while being able to reproduce more abstract settings considered in the literature. Based on this, we analyze some methods already proposed to cope with simplified saturation mechanisms, briefly discussing their underlying principles. Finally, we introduce a novel approach that takes into account the more realistic model and, at the cost of an almost negligible hardware overhead, is extremely effective in countering saturation effects.

The paper focuses on an electronic interface which can be used into piezoelectric energy scavenging systems (PESS). These systems convert the energy of mechanical vibrations into electrical energy using a piezoelectric transducer to realize a power supply for low power electronic systems. To obtain a suitable supply source an AC-DC conversion of the output signal of these transducers is needed and, since the output power level of the energy scavenger can be very low, the conversion should be as efficient as possible. This paper shows an active voltage doubler AC-DC converter for PESSs. A novel driving circuitry topology is presented; it has the advantage to be tolerant with respect to the process variations. The converter uses exclusively a fraction of the harvested energy to supply itself and a bias circuit has been designed to make the total current consumption supply independent. The simulation results show that the efficiency of the AC-DC converter can be as high as 94%. The circuit will be diffused in 0.35 mum CMOS STMicroelectronics technology.

In recent years a lot of studies focused on Energy-Scavenging Systems (ESS). An important motivation for these studies is the development of Portable Devices (PD) and of Wireless Sensor Networks (WSN). An ESS can be partitioned in two sections: the energy-scavenger itself and the electronic interface. The first one is the energy transducer while the second one is the electronic circuit which manages the energy. One of the most important objectives of the electronic interface is to realize the required ac-dc conversion. Since the output power level of the energy-scavenger can be very low, the conversion should be as efficient as possible. The goal of this paper is to design an active, high efficiency voltage doubler ac-dc converter for piezoelectric ESS which exclusively uses a fraction of the harvested energy to supply its active devices. The circuit was diffused in 0.35μm BCD6s technology. The simulation results show that it is possible to obtain a maximum efficiency of the ac-dc converter equal to 91%. Premiliminary experimental measurements were performed and the results obtained are in good agreement with simulations.

A 3.3 V CMOS line-driver is presented. The circuit is designed to be used in a serial bus system. The circuit drives a signal in the 1 MHz-16 MHz range on a 75 /spl Omega/ load with amplitude up to 2 V/sub pp/. The proposed line driver achieved a -3 dB bandwidth of about 150 MHz and performs a THD better than 40 dB for a 16 MHz 2 V/sub pp/ sinewave. The circuit is designed in a standard 3.3 V 0.35 /spl mu/m technology. It consumes about 7.5 mW and it occupies a die area of 0.02 mm/sup 2/.