This brief proposes a 7.4–9.2-GHz low-noise fractional-N differential sampling phase-locked loop (DSPLL), which features doubled phase detector (PD) gain. By using the phase-domain and voltage-domain hybrid calibration, the accumulated quantization error (Q-error) of the delta-sigma modulator (DSM) is compensated, and the locking problem caused by large sampling voltage fluctuation is solved. Meanwhile, a voltage shifting technique is introduced to adjust the locked voltage region of differential sampling PD (DSPD), which can improve the linearity of DSPLL for better calibration. Fabricated in 65-nm CMOS process, the presented DSPLL achieves measured integrated jitter of 69.09 and 73.26 fs for integer-N and fractional-N modes, respectively. The reference spur is −72.96 dBc, and the worst fractional spur is −55.26 dBc. The total power consumption is 19.2 mW at a 1.2-V supply, achieving a figure of merit jitter (FOMJ) of −249.9 dB.

In this work, a ten-way power-combined power amplifier is designed using a load modulated balanced amplifier (LMBA)-based architecture. To provide the required magnitude and phase controls between the main and control-signal paths of the LMBA, an unequal power splitter and a phase compensation network are proposed. As proof of concept, the designed power amplifier is implemented in a 45-nm SOI CMOS process. At 40 GHz, it delivers a 25.1 dBm$\text{P}_{\text {sat}}$with a peak power-added efficiency (PAE) of 27.9%. At 6-dB power back-off level, it achieves 1.39 times drain efficiency enhancement over an ideal Class-B power amplifier. Using a 200-MHz single-carrier 64-QAM signal, the designed amplifier delivers an average output power of 16.5 dBm with a PAE of 13.1% at an EVMrmsof −23.9 dB and ACPR of −25.3 dBc. The die size, including all testing pads, is only 1.92 mm2. To the best of the authors’ knowledge, compared with the other recently published silicon-based LMBAs, this design achieves the highest$\text{P}_{\text {sat}}$.

In this work, a wideband millimeter-wave (mm-wave) power amplifier (PA) is reported. To provide excellent input/output impedance matching across broadband, sufficient output power and high power-added efficiency (PAE), a balanced amplifier (BA)-based architecture is used in designing this PA. In particular, an edge-coupled quadrature coupler is designed as its RF-power-division/combination block, and its performance in terms of magnitude/phase balance error is minimized throughout a relatively wide bandwidth. A PA prototype is fabricated in 0.13-$\mu \text{m}$SiGe HBT technology and tested. Under a 1.6-V power supply, the variation of small-signal gain is less than 3 dB within 20-40 GHz, which is equivalent to more than 66% fractional 3-dB bandwidth. Within this frequency range, at least 15.8 dBm saturated output power could be delivered with the peak PAE higher than 16.8%. The designed PA supports a single-carrier 200-MHz 64-quadrature amplitude modulation (QAM) with higher than 12.8-dBm average output power, while still maintaining an error vector magnitude (EVM) below −25 dB at 30 GHz. The size of the designed compact-size PA, including all pads, is only 0.7 mm$\times1.3$mm.

The millimeter-wave (mm-wave) single-pole double-throw (SPDT) switch designed in bulk CMOS technology has limited power-handling capability in terms of 1-dB compression point (P1dB) inherently. This is mainly due to the low threshold voltage of the switching transistors used for shunt-connected configuration. To solve this issue, an innovative approach is presented in this work, which utilizes a unique passive ring structure. It allows a relatively strong RF signal passing through the TX branch, while the switching transistors are turned on. Thus, the fundamental limitation for P1dB due to reduced threshold voltage is overcome. To prove the presented approach is feasible in practice, a 90-GHz asymmetrical SPDT switch is designed in a standard 55-nm bulk CMOS technology. The design has achieved an insertion loss of 3.2 dB and 3.6 dB in TX and RX mode, respectively. Moreover, more than 20 dB isolation is obtained in both modes. Because of using the proposed passive ring structure, a remarkable P1dB is achieved. No gain compression is observed at all, while a 19.5 dBm input power is injected into the TX branch of the designed SPDT switch. The die area of this design is only 0.26 mm2.