A CMOS wideband voltage-mode fully differential all-pass filter (APF) is discussed. The APF circuit consists of three transistors, two inductors, two capacitors, and four resistors. The proposed APF employs the generic two-transistor common-source amplifier structure. Design procedures along with parasitic analysis are presented for wideband applications. The proposed APF is designed and fabricated in a 65-nm CMOS process. The operation of the proposed APF is validated by experimental and post-layout simulation results. The filter experimentally demonstrates a group delay (GD) of 59 ps at 26 GHz and it has less than 10% delay variation across a wide bandwidth of 24-29 GHz. The implemented design occupies an area of 0.09 mm2and consumes 5.1 mA from 1 V supply voltage. The noise and linearity performances of the proposed APF are validated by post-layout simulation results. The filter has a noise figure of 8.6-8.9 dB across 24-29 GHz and it achieves an input- referred IP3 of -1.14 dBm.

In this article, a synthesis methodology for analog circuit design is presented. This methodology utilizes symbolic math tools to systematically and exhaustively search for candidate analog circuits avoiding tedious manual work. The two-port network matrix representation of active devices, such as MOS transistors, paves the way for efficiently using advanced symbolic math toolboxes (e.g., in MAPLE or MATLAB) to automate the generation of new analog circuits and further investigate the effects of nonidealities and parasitics. Using this synthesis methodology new amplifiers, filters, and oscillators can be obtained starting from a predefined structure. This article aims to motivate and provide an overview of the current status of research in this area. In addition, two detailed design examples of a family of differential filters and a family of differential oscillators along with their simulations and measurement results are provided to illustrate and verify the synthesis methodology.

A multi-port spatio-temporal noise-shaping ADC is proposed to process plane waves received by spatially-oversampled antenna arrays. In the proposed multi-port ADC, the desired plane waves are processed with a spatial low-pass frequency response whereas the noise and distortion are shaped with a spatial high-pass frequency response. By employing a first-order Butterworth filter, approximately circular passbands and stopbands are achieved for the signal and the noise transfer functions, respectively. The proposed noise-shaping system is designed in the TSMC 180 nm CMOS process, with ADCs and DACs modeled as noise sources. Circuit simulation results show that the proposed system can achieve a bandwidth of 50 MHz.

The superior performance of deep learning (DL) has sent shock waves in the machine learning community. The high adoption rate of DL has set new demands on computational throughput, latency, and power efficiency of the computing infrastructure. In addition to conventional approaches to acceleration of the inference component of DL systems based on GPUs, cloud computing, ASIC/FPGAs and custom vector processors (such as tensor processing units), there is renewed interest in high-frequency analog circuits for DL inference. Analog computing is a potential candidate for meeting challenging requirements in throughput, latency and power efficiency. Because DL inference has superior noise resilience and relatively low accuracy needs (typically less than 8 bits), analog circuits can provide a promising alternative to all-digital accelerators. This paper presents early work on the design of an analog CMOS accelerator that performs analog convolution and decision operations in parallel and in real-time by pairing a high-frequency operational amplifier-based CNN filtering kernel with a rectified linear unit (ReLu) non-linearity based on an active precision rectifier circuit. The analog accelerator was designed in a 45 nm CMOS process and simulated in Cadence Spectre. Image convolution results are presented and compared with MATLAB simulations. The proposed solution also employs Xilinx RF System-on-Chip (SoC) devices based on the Xilinx ZCU1285 RFSoC platform to interface digital inputs and outputs with the proposed RF-rate analog inference accelerator.

In this paper, we propose solutions to Maxwell's equations that can be computed using analog computers. Spatially-discrete time-continuous (SDTC) algorithms running on analog computers can be potentially faster and more energy-efficient than fully-discrete numerical solvers. The implementations of fully-discrete partial differential equation (PDE) solvers on high speed digital processors, such as graphics processing units (GPUs), take many clock cycles to compute a single temporal frame of the update equation and thus have relatively low equivalent bandwidths. Our approach is to directly implement temporal recursions in continuous-time by using analog circuits. Such circuits can have bandwidths that greatly exceed the equivalent bandwidths of GPUs. In particular, we propose two analog computing methods that compute the SDTC solutions to Maxwell's equations. In addition to Maxwell's equations, such platforms can be used to accelerate other hard computational problems that involve PDEs derived from continuous-time systems. In continuous-time in Laplace domain (CTLD) method (first approach), the spatial domain partial derivatives in the governing PDE are approximated using discrete finite differences, while applying the Laplace transformation along the time dimension. The resulting spatially-discrete time-continuous update equation is utilized to design an analog circuit that can compute the continuous-time solution. The all-pass delay approximate (APDA) method (second approach) replaces the discrete-time difference operators in the standard finite difference time domain (FDTD) cell (Yee cell) using continuous-time delay operators, which can be realized using analog all-pass filters. Both methods have been simulated using ideal analog circuits in Cadence Spectre for the Dirichlet, Neumann, and radiation boundary conditions. The performance of the proposed methods have been quantified using i) mean squared differences between the results and fully-discrete FDTD simulations, and ii) the noise to signal energy ratio. The CTLD and APDA methods are able to compute the solutions to Maxwell's equations with a noise energy to signal energy ratio γ better than -26 dB and -19 dB, respectively. Both methods have been extended to design analog circuits that compute the continuous-time solution of the 1-D and 2-D wave equations. The CTLD-based 1-D and 2-D analog wave equation solvers are able to compute the solutions with γ better than -72 dB and -60 dB, respectively. The APDA-based 1-D wave equation solver is simulated with a dominant-pole model (which better approximates the non-ideal circuit behavior) along with a propagation delay compensation technique. The non-ideal analog models compute the solution with a difference smaller than -13 dB (in terms of γ). Experimental results from a simplified board-level low-frequency implementation are also presented. The key challenges toward CMOS implementations of the proposed solvers are identified and briefly discussed with possible solutions.

In this paper, the generation of differential-input differential-output second-order active filters based on a common-source differential amplifier is systematically conducted using two-port network modeling techniques which enable exploiting the power of symbolic math CAD tools. Starting from a generic two-transistor differential-pair structure, and the maximum possible number of surrounding impedances, all possible filters are derived and classified. In particular, 35 transfer functions and a total of 876 filters are found to be possible. Due to employing a $2\times 2$ transmission matrix representation of each transistor, flexibility in examining parasitic effects on the derived transfer functions is achieved and can be easily automated within the design framework. Selected filters are constructed and experimentally verified using discrete transistors. The operation of some filters is also verified with simulations using a 65-nm CMOS process.

In this paper, the generation of fully differential 2ndorder voltage-mode allpass filters is systematically studied and modeled using two-port network techniques. The proposed filters are based only on the generic two transistor common-drain differential pair and a series of surrounding RLC impedances. Five designs of possible allpass filters based on various choices of the surrounding impedances are also presented. Selected designs were verified with experimental results using discrete MOS transistors as proof of concept. One of the proposed filters was simulated in 65-nm CMOS and showed 46GHz delay-bandwidth while the delay can be electronically tuned via the bias current and independent from the pole frequency.

This paper proposes an architecture that reduces the complexity of traditional N-bit ADCs used in focal plane array (FPA) dish receivers by replacing them with multiport ADCs. The proposed ADC architecture uses a multi-dimensional (MD) noise-shaping method based on a Δ-Σ architecture for wideband RF signals that are received on the focal region of a parabolic dish/lens antenna. In the M-port noise shaping technique, the N-bit quantizers of conventional ADCs are replaced by 1-bit quantizers followed by a spatial feedback system based on a Δ-Σ architecture with spatial oversampling, which shapes the quantization noise out of the region of support (ROS) of the electromagnetic (EM) waves received from the dish. The paper discusses the case of a prime-axis pencil beam in detail for the simplified case of a linear FPA. Simulations for 2.1-5.1 GHz wideband dish signals show 16-element FPAs with oversampling ×l, ×2, and ×4 shows ADC effective number of bits (ENoB) improvements of 2.5 bits, 3.2 bits and 4.2 bits, respectively. Extensions to off-axis pencil-beams and rectangular FPAs will be considered in future work. Potential applications exist across microwave and mm-wave bands, for radio astronomy, radar, and wireless communications.

An analog all-pass filter based transfer function synthesis method is proposed for realizing multifunctional microwave active circuits. An analog realization is obtained by replacing unit sample delays in an existing digital prototype with a second-order all-pass analog filter. A novel space time array processor (STAP) and a frequency and bandwidth agile multi-band filter have been simulated using the proposed transfer function synthesis method using measured S- parameters of a fabricated 130 nm second-order CMOS all- pass filter. Simulated array patterns of the STAP beamformer show improved side-lobe performance for better interference suppression and noise rejection. The tunability of the multi-band analog filter, in terms of the center frequency and the quality factor, is verified up to 8 GHz, which has potential applications in analog microwave front-ends.

Design approaches for radio frequency (RF) analog realization of two-dimensional (2-D) network-resonant plane-wave filters are discussed. The plane-wave filters having potential applications in electronically scanned wideband beamforming scenarios operate in spatially-discrete temporally-continuous 2-D mixed-domain as described by their recursive input-output relationships. The proposed approaches imply analog array processing architectures consisting of identical interconnected analog modules (AMs). A 65 nm CMOS circuit simulation of a single AM operating at 700 MHz is used to verify the 2-D plane-wave filter response and array pattern in the first approach. An all-pass filter based time delay approximation is used to design the AMs in the second approach, where a prototype CMOS all-pass filter operating at 5.6 GHz is simulated to verify the 2-D plan-wave filter frequency response and array pattern in closed-form.

A new transimpedance amplifier (TIA) design procedure using stagger tuning with inverted transformer coils is described in this paper. A broadband TIA, realized using the proposed staggered design technique that enhances the transimpedance limit and the bandwidth while only adding small passband gain ripple, was implemented in a 0.13-μm standard CMOS process. The TIA achieves a 3-dB bandwidth of 33 GHz with a 150 fF photodiode capacitance. The TIA transimpedance gain is 43.8 dBQ with ±8 ps group-delay variation over the entire bandwidth. The circuit occupies an active area of 250 μm × 260 μm and consumes 9 mW from a 2 V supply. Despite operating with much larger photodiode capacitance, the TIA achieves the highest figure of merit, and occupies smaller area while consuming the least amount of power among previously published TIAs designed for the same data rate in similar technologies.

This paper presents a 5-bit noninterleaved time-based analog-to-digital converter (ADC), which operates at a 5-GS/s rate. The ADC is designed for the use in radio-astronomy telescopes, for which time interleaving is not acceptable. The ADC employs a dynamic, differential voltage-to-time converter, a folded-flash time-to-digital converter (TDC), and calibration circuitry. To generate reference delays, the calibration circuitry utilizes a delay-time reference network, which is designed to map the input voltage range into 16 equal time intervals that are used for the calibration of the TDC. The 65-nm CMOS ADC achieves the Signal-to-noise plus distortion ratio/spurious-free dynamic range of 27/32 dB at Nyquist, an effective number of bits (ENOB) of 4.7 bit at low frequencies and 4.1 bit at high frequencies with a power consumption of 21.5 mW at Nyquist.

RF-FPGAs and field-programmable filter arrays require tunable analog filters that can be digitally reconfigured in real-time to have several user-selected passbands and stopband notches. Such reconfigurable analog filters must operate in the microwave frequencies up to several GHz in order to meet the needs of emerging cognitive radio and reconfigurable radar front-ends. Tunable passive filters based on RF-MEMS, surface acoustic wave- and planar-technologies have been explored in the recent past to achieve this goal. In this paper, a novel RF-IC approach to design microwave filterbanks having multiple bands, each having independently tunable center frequency and quality factors, is proposed. The proposed technique is based on transfer function synthesis using first-order all-pass filters as a building block. Using measured data from a current-mode 130-nm CMOS allpass filter implementation, the feasibility of multi-band tunable filter arrays is simulated with a tuning range of 4 GHz.

A CMOS wide-bandwidth first-order current-mode all-pass filter (APF) is discussed. The circuit consists of one transistor, a resistor, a grounded inductor, and a load. When used with a current mirror as the load, the current-mode filter exhibits a high output impedance, which is advantageous from an integration point of view and enables this configuration to be cascaded with current-mode circuits. The operation of the proposed circuit is experimentally validated. The APF implemented in IBM 0.13-μm CMOS was measured to have the pole-zero pair located at 8.32 GHz and to achieve a 55 ps group delay while consuming 19 mW from a 1.5-V supply. This paper experimentally demonstrates a CMOS APF that operates at multi-GHz frequencies and achieves the highest delay-bandwidth products of the published CMOS first-order APFs known to the authors.

This paper presents a 12.5-Gb/s on-chip oscilloscope (OCO) circuit to measure eye diagrams and jitter histograms of high-speed digital signals. The proposed circuit adopts a novel architecture to capture both single-ended and differential signals. In addition, it is capable of measuring the eye openings and jitter of the input signals without the need to construct the whole eye diagram which makes it a suitable candidate for eye-opening monitor circuits. An asynchronous sampling technique and an efficient algorithm are employed in this research to decrease the area of the OCO as well as its processing time. The proposed circuit is fabricated in a 65-nm CMOS technology and the measurement results show sub-picosecond resolution when the input signals consist of a 10-GHz clock signal and a 12.5-Gb/s pseudorandom binary sequence. The OCO circuit has a power consumption of 1.9 mW, and its core area is 40 × 60 μm.

This paper presents a 4-bit noninterleaved single-clock-phase 10-GS/s analog-to-digital converter (ADC) fabricated in TSMC 65-nm CMOS technology. The ADC is realized using novel switched dynamic comparators (SDCs), which alleviate the clock-frequency-limiting long regeneration time in prior-art dynamic comparators, and avoid the phase-skew issue associated with time-interleaved ADCs that limits their signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range. The SDC employs a reference-free topology and has no static power consumption. The trip voltage errors of the SDCs are corrected by an efficient on-chip digital background calibration technique. The noninterleaved ADC presents an estimated 100 fF of capacitance at its input, excluding bondpad capacitance, with most of it contributed by the traces leading to the ADC and the shielding structures associated with the input traces. At 10-GS/s sampling rate, the prototype ADC achieves an SNDR of 24.9 dB [3.84 effective number of bit (ENOB)], and 23.4 dB (3.59 ENOB) at low input signal frequencies and Nyquist, respectively. The chip consumes 104 mW from a 1.3 V supply. The ADC has an active area of 0.1 mm2.

An electronically steerable broadband radio frequency (RF) filter-sum beamforming filter using 1st-order all-pass filters is proposed. The beamforming filter has the 2-D transfer function Ha (zx, sct), which uses M-section cascaded 1st-order all-pass filters and analog combiners as building blocks. Beam steering is achieved by tuning the group delay of the all-pass filters via a control voltage. For beam directions ψ ≤ 20ofrom array broadside, M = 1 provides close to ideal broadband response, and 120°. The array factor of the beamformer is evaluated using 65 nm CMOS BSIM 4 simulations of the all-pass filters and a 4-channel RF combiner for a linear antenna array of 4 antennas and is shown to provide steerable beams at 1 GHz. The CMOS simulations verify a broadband response from DC to 1 GHz.

In this paper, an inductorless broadband linear-in-dB Variable-Gain Amplifier (VGA) circuit for use in the Square Kilometer Array (SKA) is presented. A two-transistor topology, which realizes a linear-in-dB function, is used to design a differential VGA. The VGA is both input and output power matched to 100Ω differential sources and loads. The design is fabricated in ST 65nm CMOS technology with a 1V power supply. Measurement results show that the VGA has a 25dB variable gain range, input P1dB of -25dBm to -32dBm with control voltage ranging from 0.5V to 1.0V, and is designed to work in a frequency range from 0.7GHz to 1.4GHz, which is the frequency range of the mid-band SKA receiver. The total power consumption of the VGA is 1mW with another 6mW consumed by an input-match circuit and 1mW consumed by an output buffer circuit.

A two-dimensional (2D) space-time (ST) delay operator D2DST[·] and a novel discrete-space-continuous-time (DSCT) CMOS VLSI implementation at radio frequency (RF) is proposed. The proposed delay operator is able to delay 2D ST antenna array signals along space and time and can be used as a building block in 2D ST array processing algorithms. A 2D non-separable DSCT transfer function (TF), ΦApp(zx, sct) is used to approximate the ideal 2D ST delay represented by the 2D TF equation. A passive frequency planar transformation followed by bilinear transform along spatial dimension is used to derive ΦApp(zx, sct) starting from a 1D passive all-pass prototype. The 2D delay D2DST[·] is proposed to be realized using an array of identical analog modules (AMs). A CMOS VLSI circuit operating at RF is proposed for each AM. Magnitude and phase frequency responses of a single AM operating at 1 GHz is obtained using 65 nm TSMC CMOS simulations in Cadence and compared with the theoretical responses. The 2D phase frequency response of D2DST[·] is obtained using the CMOS simulated response of a single AM.

A continuous-time discrete-space 2D IIR fan filter is proposed for ultra-wideband beamforming for uniform linear arrays of antennas. The proposed signal-flow-graph replaces sampled unit-delays in a 2D FIR digital prototype fan filter using time-delays of the same duration using an ideal delay line. Thereafter, ideal delays are approximated using an RC-active VLSI circuit consisting of high-order all-pass filters aimed at the 90 nm CMOS technology. The paper covers transfer function design, 2D input spectra in continuous-time, delay approximation, CMOS all-pass circuits and simulation. Finally, a prototype with fan axis directed along θ = 30° (from temporal frequency axis) and half fan angle ε = 6° is simulated and the frequency response from DC to 3.6 GHz is obtained using data from a BSIM4 model of a 10th- order all-pass filter. The proposed novel analog 2D fan filters are free of aliasing, quantization noise, switching power consumption, and do not require an array of high-speed analog-to-digital converters.

A CMOS low noise amplifier (LNA) is proposed for a proof-of-concept design of the square kilometer array (SKA) radio telescope. A novel variation on a well-known source-degenerated LNA topology is introduced that allows tuning of the power match centre frequency independently from the frequency at which the LNAs noise figure approaches its minimum noise. The 0.7-1.4 GHz LNA designed in 0.18mum CMOS achieves better than 11 dB return loss with a noise temperature of 40 K, provides a power gain of 17 dB and IP1dB of -10dBm while consuming 50 mW of power from a 1.8 V supply. The design procedure of the LNA is presented and performance of the LNA is compared with previously published results