Modern field programmable gate arrays like Altera's Stratix Series have adopted the adaptive logic module (ALM) structure due to its potential performance and area advantages. An ALM can implement a single logic function or can be fractured into two smaller lookup tables (LUTs). In this paper, we propose an ALM mapping algorithm, ALMmap, for area minimization with bounded depth. We revamp the traditional iterative cut-based mapping flow and introduce a procedure for bounded depth mapping generation with dynamic area recovery that effectively combines cut selection, mapping, and area recovery together. In addition, we introduce a new procedure for computing cut set for ALM minimization under a depth constraint. The notion of area flow which has been used successfully for cut selection to reduce LUT count is revised for cut selection to reduce ALM count. ALMmap obtains depth optimal solutions that are 25.6% and 11.6% smaller, on average, than those produced by a classical mapper and WireMap, respectively.

We propose a power-driven flip-flop (FF) merging and relocation approach that can be applied after conventional timing-driven placement and before clock network synthesis. It targets to reduce the clock network size and thus the clock power consumption while controlling the switching power of the nets connected to the FFs by selectively merging FFs into multibit FFs and relocating them under timing and placement density constraints. The experimental results are very encouraging. For a set of benchmarks, our approach reduced the switching capacitance of clock network by 36%-43% after gated clock tree synthesis. Finally, the total switching capacitance of clock network and nets connected to the FFs is reduced by 24%-29%.

We propose a power-driven flip-flop merging and relocation approach that can be applied after conventional timing-driven placement and before clock network synthesis. It targets to reduce the clock network size and thus the clock power consumption, as well as the switching power of the nets connected to the flip-flops by selectively merging flip-flops into multi-bit flip-flops and relocating them under timing and placement density constraints. The experimental results are very encouraging. For a set of benchmarks, our approach reduced the clock wirelength by 30 to 50%. Meanwhile, the switching power of signal nets connected to the flip-flops were reduced by 2 to 43%.