Hardware Trojans (HTs) are regarded as a security threat in the information society. HTs are unintentionally injected into LSI circuits by untrusted entities before the chip fabrication. HTs trigger malicious operations such as information leakage without designers noticing their operations. This paper proposes fine-grained power domain partitioning, which is a circuit design technique for detecting HT activities. This paper assumes a scenario where a fab injects HTs into the taped-out layout data and that circuit designers test the presence of HTs by using side-channel information (power consumption) of fabricated chips. Fine-grained power domain partitioning decomposes the power domain of target circuit into multiple power domains, enabling to effectively measure the small power consumption introduced by activities of tiny HTs. The measurement result using an HT-injected Advanced Encryption Standard (AES) circuit with fine-grained power domain partitioning shows that HTs can be detected.

It is well-known that operating transistors in low-temperature environments improves their characteristics. This has led to the expansion of integrated circuit (IC) applications at low temperatures, including high-performance computers and controllers for quantum computers. On the other hand, hardware Trojans (HTs) pose a severe concern, threatening the authenticity of ICs. This study proposes a new HT circuit, referred to as Cryo-HT, that can be activated by the increased discharge time of a metal-oxide-semiconductor (MOS) capacitor at low temperatures. We fabricated an advanced encryption standard (AES) circuit with Cryo-HT using 180 nm process technology. We demonstrate that Cryo-HT is not activated at room temperature but activates at 213 K to reveal the AES encryption key.

The threat of information leakage by Side-Channel Attacks (SCAs) using ElectroMagnetic (EM) leakage is becoming more and more prominent for crypto circuits. This paper models tamper resistance to EM SCAs on voltage-scaled crypto circuits. It is well known that if the supply voltage is donwscaled, attackers need to acquire more EM traces to extract secret key information in crypto circuits. Therefore, crypto circuits can process more data safely. However, their supply voltage dependence is not fully studied. This paper thus firstly models voltage dependence of the strength in the EM emission from crypto circuits. Then, this paper proposes the tamper resistance model which analytically expresses the relationship between the supply voltage and the minimum traces to disclosure based on test vector leakage assessment. This helps consider to optimize the trade-off relationship between encryption performance and tamper resistance to the information leakage. The proposed models are validated by measurement results using an Advanced Encryption Standard (AES) circuit with a 180-nm process technology.

Smart traffic monitoring at intersections which exploits three-dimensional light detection and ranging (LiDAR) sensor networks is a promising technique for achieving a safe and secure society. One challenge for widely spreading these systems is to effectively aggregate massive point cloud data generated by multiple LiDAR sensors installed at every corner of intersections with a limited cost and a limited communication bandwidth. To this end, this paper proposes a lightweight point cloud compression method for real-time smart traffic monitoring. The proposed method enables tiny low-cost processors installed at every LiDAR sensor to detect moving parts of a point cloud from point could data in real time. By sending compressed data of moving parts of a point cloud only to edge servers, the communication bandwidth is saved, which helps edge servers to analyze them for preventing traffic accidents in real time. Experimental results using the KoPER intersection dataset show that the average detection rate over 1,200 frames of data is around 95%. The processing time per frame is about 5.4 ms with a commercial edge-oriented processor, which is less than typical frame rates of modern LiDAR sensors. In addition, point could compression ratio of the proposed method is approximately 3.5 times better than that without the moving part detection technique.

Voltage scaling is one of the most promising approaches for energy efficiency improvement but also brings challenges to fully guaranteeing stable operation in modern VLSI. To tackle such issues, we further extend the DependableHD to the second version DependableHDv2 , a HyperDimensional Computing (HDC) system that can tolerate bit-level memory failure in the low voltage region with high robustness. DependableHDv2 introduces the concept of margin enhancement for model retraining and utilizes noise injection to improve the robustness, which is capable of application in most state-of-the-art HDC algorithms. We additionally propose the dimension-swapping technique, which aims at handling the stuck-at errors induced by aggressive voltage scaling in the memory cells. Our experiment shows that under 8% memory stuck-at error, DependableHDv2 exhibits a 2.42% accuracy loss on average, which achieves a 14.1× robustness improvement compared to the baseline HDC solution. The hardware evaluation shows that DependableHDv2 supports the systems to reduce the supply voltage from 430 mV to 340 mV for both item Memory and Associative Memory, which provides a 41.8% energy consumption reduction while maintaining competitive accuracy performance.

Voltage scaling is one of the most promising approaches for energy efficiency improvement but also brings challenges to fully guaranteeing the stable operation in modern VLSI. To tackle such issues, we propose DependableHD, a learning framework based on HyperDimensional Computing (HDC), which supports the systems to tolerate bit-level memory failure in the low voltage region with high robustness. For the first time, DependableHD introduces the concept of margin enhancement for model retraining and utilizes noise injection to improve the robustness, which is capable of application in most state-of-the-art HDC algorithms. Our experiment shows that under 10% memory error, DependableHD exhibits a 1.22% accuracy loss on average, which achieves an 11.2× improvement compared to the baseline HDC solution. The hardware evaluation shows that DependableHD supports the systems to reduce the supply voltage from 400mV to 300mV, which provides a 50.41% energy consumption reduction while maintaining competitive accuracy performance.

Hyper-Dimensional (HD) computing is a brain-inspired learning approach for efficient and fast learning on today's embedded devices. HD computing first encodes all data points to high-dimensional vectors called hypervectors and then efficiently performs the classification task using a well-defined set of operations. Although HD computing achieved reasonable performances in several practical tasks, it comes with huge memory requirements since the data point should be stored in a very long vector having thousands of bits. To alleviate this problem, we propose a novel HD computing architecture, called DistriHD which enables HD computing to be trained and tested using binary hypervectors and achieves high accuracy in single-pass training mode with significantly low hardware resources. DistriHD encodes data points to distributed binary hypervectors and eliminates the expensive item memory in the encoder, which significantly reduces the required hardware cost for inference. Our evaluation also shows that our model can achieve a$27.6\times$reduction in memory cost without hurting the classification accuracy. The hardware implementation also demonstrates that DistriHD achieves over$9.9\times$and$28.8\times$reduction in area and power, respectively.

This demonstration proposes a scheme that suppresses the data size of a 3D-image sensing network by adaptively filtering low-importance points, such as the points of floors and ceilings when the task is to track pedestrians. The adaptive filter can be dynamically changed to further reduce the amount of data if it is difficult for packets to reach the edge computer. We evaluate the proposed scheme through experiments and demonstrate that it performs better than benchmark schemes in terms of prompt arrival of the data.

A tamper-resistant logical operation method based on integrated nanophotonics is proposed focusing on electromagnetic side-channel attacks. In the proposed method, only the phase of each optical signal is modulated depending on its logical state, which keeps the power of optical signals in optical logic circuits constant. This provides logic-gate-level tamper resistance which is difficult to achieve with CMOS circuits. An optical implementation method based on electronically-controlled phase shifters is then proposed. The electrical part of proposed circuits achieves 300 times less instantaneous current change, which is proportional to intensity of the leaked electromagnetic wave, than a CMOS logic gate.

In convolutional neural networks (CNNs), data movement inside convolution layers between memory and PEs is most energy dominant. This paper proposes a convolution processing dataflow that reduces both the number of memory accesses and the on-chip buffer capacity for convolution operations. Based on the dataflow, we design an on-chip buffer-minimized CNN accelerator. Compared with the state-of-the-art CNN accelerator, the proposed CNN accelerator utilizes 2.30 times less on-chip buffer and 2.18 times energy efficiency to achieve the same data throughput under Alexnet. The proposed architecture is able to achieve higher data throughput with the almost constant on-chip buffer capacity.

Optical circuits using nanophotonic devices attract significant interest due to its ultra-high speed operation. As a consequence, the synthesis methods for the optical circuits also attract increasing attention. However, existing methods for synthesizing optical circuits mostly rely on straight-forward mappings from established data structures such as Binary Decision Diagram (BDD). The strategy of simply mapping a BDD to an optical circuit sometimes results in an explosion of size and involves significant power losses in branches and optical devices. To address these issues, this paper proposes a method for reducing the size of BDD-based optical logic circuits exploiting wavelength division multiplexing (WDM). The paper also proposes a method for reducing the number of branches in a BDD-based circuit, which reduces the power dissipation in laser sources. Experimental results obtained using a partial product accumulation circuit in parallel multipliers demonstrates significant advantages of our method over existing approaches in terms of area and power consumption.

A cross-coupled inverter which is an essential element of on-chip memory subsystems plays an important role in synchronous LSI circuits. In this paper, an analytical stability model for a cross-coupled inverter operating in a sub-threshold voltage region is proposed. The proposed model analytically shows that the minimum operating voltage of the cross-coupled inverter distributes normally in a high-s region if the distribution of the threshold voltage is Gaussian. The minimum supply voltage at which the yield of the cross-coupled inverter becomes a specific value can be accurately derived by a simple calculation using the model. Monte-Carlo simulation assuming a commercial 28 nm process technology demonstrates the accuracy and the validity of the proposed model. Based on the model, this paper shows strategies for variation tolerant memory design.

Near-threshold computing has emerged as a promising solution for drastically improving the energy efficiency of microprocessors. This paper proposes architectural-level statistical static timing analysis (SSTA) models for the near-threshold voltage computing where the path delay distribution is approximated as a lognormal distribution. First, we prove several important theorems that help consider architectural design strategies for high performance and energy efficient near-threshold computing. After that, we show the numerical experiments with Monte Carlo simulations using a commercial 28-nm process technology model and demonstrate that the properties presented in the theorems hold for the practical near-threshold logic circuits.