A harmonic cancellation technique based on a phase manipulation technique is presented for Ku-band voltage-controlled oscillators (VCO), achieving significant phase noise reduction, especially at the$1/f^{3}$region. The proposed VCO incorporates an auxiliary PMOS transistor with dynamically controlled biasing to generate additional high-order components to compensate for the intrinsic phase difference between the high-order harmonic components of the main PMOS and NMOS cross-coupled transistors, establishing the required$180^{o}$phase difference ($\Delta \theta $) between them. The alignment, facilitated by the proposed technique, significantly suppresses the undesired high-order harmonic components entering the tank’s capacitive path and disturbing its natural frequency. The proposed VCO is fabricated in 65nm CMOS technology, achieving a phase noise of −33.78 dBc/Hz at 1 kHz and -112 dBc/Hz at 1 MHz. The phase noise improvement reaches 5.56 dB at the$1/f^{3}$region compared to a conventional complementary VCO. With a low power consumption of 4.5 mW, the proposed VCO achieves an excellent figure-of-merit (FoM) of −188.4 dBc/Hz with a tuning range of 1.1 GHz (8.1%) operating from 13 GHz to 14.1 GHz.

Advanced Internet-of-Things (IoT) devices are increasingly used in high-temperature environments, such as automotive, aerospace, defense, and industrial applications. High-temperature voltage references are crucial for these systems. This paper presents two topologies designed for high-temperature operation. The first topology minimizes design costs by using a replica branch to decouple leakage from the core, reducing its impact on the reference voltage. The second topology optimizes the operating temperature by employing one-stage amplifiers as buffers to handle junction leakage while maintaining body voltage. Both designs are fabricated in a 180 nm CMOS process. The first design supports operation up to 140∘C with an average temperature coefficient (TC) of 70 ppm/∘C, while the second design operates up to 170∘C with a TC of 64 ppm/∘C. The designs also exhibit line sensitivities of 0.46 %/V and 0.31 %/V, PSRRs of –37.8 dB and –38.3 dB at 100 Hz, and power consumption of 111 pW and 136.8 pW at room temperature, respectively.

This article presents adiabatic data transmitters using stepwise driving to improve the energy efficiency of low data-rate sensor nodes beyond theCV2limitation. Stepwise driving is applied to NRZ and PAM-4 modulations, supporting data rates of hundreds of Mb/s, required by micro-controller peripheral I/O interfaces in sensor nodes. Fabricated in 22nm CMOS, the proposed transmitter drivers achieve over 64% energy savings at 200 Mb/s compared to conventionalCV2drivers.

This brief proposes a resistor-less bandgap reference (BGR) based on a leakage-based proportional-to-absolute-temperature (PTAT) scheme. The effect of process variations on the current is mitigated by employing self-biased current-limiting MOS transistors. The bias voltages needed for approximating a large resistance can be obtained from a single branch by placing threshold-sampling transistors on top of the BGR output. The fabricated BGR in 0.18-$\mu \text{m}$CMOS occupies an active area of 0.035 mm2and consumes 20.5 nW, and it shows a standard deviation of 0.68% at untrimmed reference voltages.

This paper presents a sub-10 nW bandgap reference (BGR) circuit that implements both voltage and current references in one circuit. The BGR circuit was implemented with a 0.18μm CMOS process and generates voltage and current references of 1.238 V and 6.64 nA while consuming 9.3 nW. The voltage and current references show standard deviations of 0.43 % and 1.19 % with temperature coefficients of 26 ppm/°C and 283 ppm/°C, respectively.

This paper presents an amplifier-less and digital-intensive current-to-digital converter for biosensors. The proposed circuit achieves a first-order noise shaping of the quantization error without any continuous-time feedback circuit. Also, it minimizes static power consumption by employing a single-ended current-steering digital-to-analog converter (DAC) which flows only the same current as the input. The effect of dynamic switching noise become input-independent constant by adopting switching averaging algorithm. The implemented circuit in 0.35pm CMOS converts an input range of 2.8pA to 15b digital output in about 4ms, while consuming 16.8pW.