Online surrogate model-assisted evolution algorithms (SAEAs) are very efficient for analog/RF circuit optimization. To improve modeling accuracy/sizing results, we propose an efficient transfer learning-assisted global optimization (TLAGO) scheme that can transfer useful knowledge between neural networks to improve modeling accuracy in SAEAs. The novelty mainly relies on a novel transfer learning scheme, including a modeling strategy and novel adaptive transfer learning network, for high-accuracy modeling, and greedy strategy for balancing exploration and exploitation. With lower optimization time, TLAGO can have a faster rate of convergence and more than 8% better performances than GASPAD.

This paper proposes a two-step fine-tuning assisted layout sizing (FALS) scheme with an efficient post-layout sampling feature, the key of which is to reuse abundant and cheap schematic information with Transfer Learning for quickly pruning design space and achieving global optimization. The innovation is that FALS is the first work to integrate the advantages of two-step optimization and high-accuracy model-based local optimization. The same optimization results can be achieved by FALS with significantly 10× less total run-time than the conventional DE.

In recent years, electronic design automation methodologies based on hierarchical multilevel bottom-up (BU) design approaches are emerging and successfully applied for RF system design. In this article, we propose a design automation methodology for the synthesis of millimeter-wave (mm-wave) systems via BU approaches, including sizing and layout generation. First, uniformly sampled passive and active component libraries with prepared layouts and S-parameter files are constructed during the offline preparation stage. Second, the BU sizing from the device level to the system level has been demonstrated via multiobjective optimization algorithms, while an improved Euclidean mapping strategy is proposed to efficiently search over circuit-level Pareto-optimal fronts (POFs) in the system-level optimization. Third, the parameterized DRC/LVS clean layout can be hierarchically generated for the system-level POFs. Compared to flat optimization at the system level, the proposed method greatly reduces the size of the search space with the highest accuracy possible and can be used for the synthesis of complex mm-wave systems. The proposed method achieves a$10\times $runtime speedup in the system-level optimization with better optimization results.

In this article, we propose an efficient surrogate-assisted constrained multiobjective evolutionary algorithm for analog circuit sizing via self-adaptive incremental learning. The proposed approach reduces the total optimization time in four aspects. First, by reusing the previously trained models, the incremental learning technique is introduced to reduce the time complexity of training the Kriging model from$O(n^{3})$to$O(n^{2})$, where$n$is the number of training points. Second, a self-adaptive strategy to control when to update hyperparameters is proposed to further reduce the training time of the Kriging model. Third, our method is driven by prescreening the most promising population instead of internal optimization which saves the prediction time of the Kriging model. Fourth, the maximin distance-based expected improvement matrix criterion is introduced as the acquisition function to formulate multiple objectives into a scalar function, reducing the sorting time to rank population. Experimental results on three real-world circuits demonstrate that compared with the state-of-the-art multiobjective Bayesian optimization, our method achieves a speedup of up to$13\times $in total runtime without surrendering optimization results. To be more specific, our method reduces the training time of the Kriging model by 96%, the prediction time by 99%, and the sorting time to rank population by up to 92%. Compared with NSGA-II, there is up to$6\times $speedup in terms of the total runtime with better results.

A self-clocked unified voltage-and-frequency regulator (UVFR) is proposed to provide a highly correlated voltage-and-clock pair and to guarantee error-free operation of an arbitrary in-order executed digital load. Built on a digital low-dropout regulator (D-LDR), the unified control loop is highly synthesizable and adaptively clocked to achieve both fast transient response and low quiescent current. Replica frequency-locked loops (FLLs) and hysteresis switching logic (HSL) are employed to compensate for the built-in offset of conventional beat-frequency (BF) quantization and provide calibration-free regulation to tolerate global and random variations. Fabricated in a 65-nm CMOS process, the proposed UVFR reduced the voltage undershoot by 25%, reduced the steady-state offset by 84%, and achieved a 5.9X wider adaptive clocking range compared to the baseline with the help of our proposed replica FLLs and HSL.

This work presents a white-box modeling of the electromagnetic (EM) leakage from an integrated circuit (IC) to develop EM side-channel analysis (SCA)-aware design techniques. A new digital library cell layout design technique is proposed to minimize the EM leakage and is evaluated using a high-frequency structure simulator (HFSS)-based framework. Backed by our physics-based understanding of EM radiation, the proposed double-row power grid-based digital cell layout design shows$>5\times $reduction in the EM SCA leakage compared to the traditional digital logic gate layout design. Furthermore, exploiting the magneto-quasistatic (MQS) regime of operation of the EM leakage from the CMOS circuits, the HFSS-based framework is utilized to develop a pre-silicon (Si) EM SCA evaluation technique to assess the vulnerability of cryptographic implementations against such attacks during the design phase itself.

Implementing a monolithic highly efficient ultralow photovoltaic (PV) power harvesting system is pivotal for smart nodes of Internet of things (IOT) networks. This paper proposes a fully integrated harvesting system in 0.18-μm CMOS technology. Utilizing a small commercial solar cell of 2.5 cm2, the proposed system can provide 0-29 μW of power, which is much higher than the commonly used passive radio-frequency identification devices in IOT application. The hill-climbing maximum power point tracking algorithm is developed in an energy-efficient manner to tune the input impedance of the system and guarantee adaptive maximum power transfer under wide illumination conditions. The detailed impedance tuning approach is implemented with a capacitor value modulation to eliminate the quiescent power consumption as well as to achieve a higher efficiency than the traditional pulse-frequency modulation scheme. A supercapacitor is utilized for buffering, energy storing, and filtering purposes, which enables more functions of the IOT smart nodes such as active sensing and system-on-chip (SOC) signal processing. The output voltage ranges between 3.0 and 3.5 V for different device loads, such as sensors, SOC, or wireless transceivers. The measured results confirm that this PV harvesting system achieves both ultralow operation capability under 20 μW and a selfsustaining efficiency of 89%.