The paper proposes a method for guard-band customization to improve the energy efficiency of commercial FPGA. We deploy custom delay-based sensors alongside any user design to indirectly monitor, in real-time, the functional integrity of the target under voltage scaling. We develop a reliable sensing mechanism and regulate the FPGA operation by holistically considering process, voltage, and temperature variations during run-time. Tests with Xilinx Zynq SoC FPGAs and real benchmarks show significant power savings, in the area of 16-27%, while preserving nominal timing performance for only 1.6% resource overhead.

In the current work, we study the process variability of logic, interconnect, and arithmetic/DSP resources in commercial 16-nm FPGAs. We create multiple, soft-macro sensors for each distinct resource under evaluation, and we deploy them across the FPGA fabric to measure intra-die variation, as well as across multiple FPGAs to measure inter-die variation. The derived results are used to create device-signature variability maps characterizing the distribution of variability across the die. Our study includes decoupling of variability to systematic and stochastic parts, exploration of variability under various voltage and temperature conditions and correlation analysis between the variability maps of the different resources. Furthermore, we scrutinize the impact of variability on the performance of actual test circuits and correlate the retrieved results with the sensor-based maps. Our experimental results on four Zynq XCZU7EV FPGAs showed significant intra- and inter-die variability, up to 7.8% and 8.9%, respectively, with a small increase under certain operating conditions. The correlation analysis demonstrated a strong correlation between the logic and arithmetic resources, whereas the interconnects showed a slightly weaker correlation in specific devices. Finally, a relatively moderate correlation was calculated between the variability maps and performance of test circuits due their dissimilar operating behavior versus our sensors.

In this work we introduce a method to improve the energy efficiency of the FPGA devices by reducing the pessimistic operation guardbands posed by the commercial EDA tools. The proposed method bases on a voltage scaling scheme that reliably decreases the supply voltage. We deploy a uniform network of delay-based sensors across the fabric of the FPGA to sense all process, voltage and temperature variation (PVT) effects. The delay of all the sensors is calibrated to match the worst critical path delay of the target application. In that respect, the monitoring of the sensor network enables the indirect assessment of the functional integrity of the target application. The distributed placement of the sensors provides the desired sensitivity with appropriate granularity across the fabric and allows us to consider the worst-case scenario. The sensor network is integrated during the development cycle as ready-to-use software IP with negligible resource overhead, for example, 1-2% of a Zynq XC7Z020 FPGA for 10 sensors. The sensitivity of the sensors to all PVT variations and the correlation with the application operation is verified through extensive testing by using multiple FPGAs and realistic benchmarks. The aforementioned approach facilitates a closed-loop voltage scaling scheme to regulate the supply voltage and reduce the power of the system. In our experiments on a set of 28nm Xilinx XC7Z020 SoC FPGAs and realistic digital signal processing (DSP) benchmarks, we demonstrate up to 27.2% decrease in power for 13% decrease in voltage, while retaining the nominal timing performance.

Process variability is a challenging fabrication issue impacting, mainly, the reliability and performance of chips. Variability is already present in current technology nodes and is expected to become even more significant in the future. In this work, we focus on the study of performance variation in 16nm FinFET FPGAs. We devise a comprehensive assessment methodology based on multiple programmable sensors with diverse resource and delay characteristics. Additionally, we consider various voltage and temperature conditions and decouple variability to systematic and stochastic. The experimental results on Zynq XCZU7EV show up to 7.3% intra-die variation increasing to 9.9% for certain operating conditions. Our approach demonstrates that logic and interconnect resources present different variability, slightly uncorrelated, which highlights the necessity and way towards more sophisticated mitigation methods/tools.

The mitigation of process variability becomes paramount as chip fabrication advances deeper into the sub-micron regime. Conservative guard-bands result in considerable performance loss, while most low-level solutions impede dynamic customization at application level. This paper exploits the existing process variability of commercial off-the-shelf FPGAs to improve the operating frequency of a design, in-the-field, at anytime during the lifetime of a chip. We begin by measuring variability in prevalent FPGAs and assessing its impact on the performance of common DSP benchmarks. For the former, we develop a custom sensing network of Ring-Oscillators to generate detailed 2D maps per chip. For the latter, we perform intensive testing and statistical analysis to establish the relation between variability maps and benchmark frequencies. Accordingly, we propose a framework to automatically characterize the user's devices, place the design on the most efficient region, and scale its frequency based on user requirements and functional verification. Experimental results on 20 FPGAs of 28 nm Xilinx technology show up to 13 percent intra-die and 30 percent inter-die variability; with limited cost, our framework provides 10-14.7 percent average gain by exploiting such variability, or up to 56-138 percent by also customizing the guard-band.

Increased mobile autonomy is a vital requisite for future planetary exploration rovers. Stereo vision is a key enabling technology in this regard, as it can passively reconstruct in three dimensions the surroundings of a rover and facilitate the selection of science targets and the planning of safe routes. Nonetheless, accurate dense stereo algorithms are computationally demanding. When executed on the low-performance, radiation-hardened CPUs typically installed on rovers, slow stereo processing severely limits the driving speed and hence the science that can be conducted in situ . Aiming to decrease execution time while increasing the accuracy of stereo vision embedded in future rovers, this article proposes HW/SW co-design and acceleration on resource-constrained, space-grade FPGAs. In a top-down approach, we develop a stereo algorithm based on the space sweep paradigm, design its parallel HW architecture, implement it with VHDL, and demonstrate feasible solutions even on small-sized devices with our multi-FPGA partitioning methodology. To meet all cost, accuracy, and speed requirements set by the European Space Agency for this system, we customize our HW/SW co-processor by design space exploration and testing on a Mars-like dataset. Implemented on Xilinx Virtex technology, or European NG-MEDIUM devices, the FPGA kernel processes a 1,120 × 1,120 stereo pair in 1.7s−3.1s, utilizing only 5.4−9.3 LUT6 and 200−312 RAMB18. The proposed system exhibits up to 32× speedup over desktop CPUs, or 2,810× over space-grade LEON3, and achieves a mean reconstruction error less than 2cm up to 4m depth. Excluding errors exceeding 2cm (which are less than 4% of the total), the mean error is under 8mm.

As technology node scales-down and process variability increases, the vendors impose even more conservative guard-bands to prevent potential malfunction of their microchips. However, this approach introduces considerable amounts of unexploited performance to individual chips, which can be harvested by developing novel customization tools. In the current work, we focus on the exploitation of process variability in modern FPGA chips to provide more energy efficient solutions. We propose a framework that i) generates variability maps characterizing the energy efficiency of commercial chips and ii) combines voltage and frequency scaling to limit the power dissipation of any given design for a given set of performance constraints. Experimental results on Zynq XC7Z020 28nm FPGAs show that the developed framework achieves up to 28.3% power reduction while maintaining the performance and functional integrity of realistic benchmarks. Moreover, by selecting the most efficient chip, we achieve up to 5.1% additional power savings.

Carrier phase recovery (CPR) for phase noise mitigation is a vital part of modern coherent optical systems. As higher order M-QAM modulation formats are being employed to increase network capacity, CPR complexity grows as well, and more powerful chips are needed to cope with the advanced DSP. In this paper we present an FPGA-based flexible architecture of the Nonlinear Least Squares (NLS) CPR algorithm, targeting present-day and future generation systems. We describe optimization approaches at the algorithmic and HW levels to facilitate HW efficiency, while we combine multiple parallelization techniques to achieve high-throughput processing. Considering various FPGA devices, we perform fine-grain exploration with respect to cost, throughput and accuracy to support up to 64 GBd 16-QAM links with less than 1 dB SNR penalty.

Process variability is known to be increasing with technology scaling in IC fabrication, thereby degrading the overall performance of the manufactured devices. The current paper focuses on the variability effect in FPGAs and the possibility to boost the performance of each device at run-time, after fabrication, based on the individual characteristics of this device. First, we develop a sensing infrastructure involving a wide network of customized ring oscillators to measure intra-chip and inter-chip variability in 28nm FPGAs, i.e., in eight Xilinx Zynq XC7Z020T-1CSG324 devices. Second, we develop a closed-loop framework based on dynamic reconfiguration of clock tiles, I/O data sniffing, HW/SW communication, and verification with test vectors, to dynamically increase the operating frequency in Zynq while preserving its correctness. Our results show intra-chip variability in the area of 5.2% to 7.7% and inter-chip variability up to 17%. Our framework improves the performance of example FIR designs by up to 90.3% compared to the SW tool reports and shows speed difference among devices by up to 12.4%.

Recent advances in photonics and imaging technology allow the development of cutting-edge, lightweight hyperspectral sensors, both push-broom/line-scanning and snapshot/frame. At the same time, emerging applications in robotics, food inspection, medicine and earth observation are posing critical challenges on real-time processing and computational efficiency, both in terms of accuracy and power consumption. In this direction, in the current paper, we accelerate hyperspectral processing kernels by utilizing FPGAs, i.e., Zynq-7000 SoC, to perform similarity-based matching of spectral signatures. We propose a custom HW architecture based on multi-level parallelization, modularity, and parametric VHDL coding, which allows for in-depth design space exploration and trade-off analysis. Depending on configuration, our implementation processes 22-107 Megapixels per second providing an acceleration of 40-355x vs Intel-i3 CPU and 360-104x vs the embedded ARM Cortex A9, whereas the overall detection quality ranges from 56% to 97% when evaluated with multiple objects and images of 285 spectral channels.