Demo Data from EDBT 2026 / reviewers in the wild / expert
Kyndylan Nienhuis
dblp:160/7732
· DBLP profile ↗
5ranked-venue papers
2as first author
0since 2021 · last 2020
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Software engineering, systems software and programming languages · 4 · 1 first-authorSecurity and privacy · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Software engineering, system software, and programming languages
4 papers |
Concurrent programming · 48% Programming languages and type systems · 41% Program verification · 5% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 100% | |
| Network and information security
1 paper |
Hardware security and side channels · 100% |
Topics — the 13 heaviest of 13, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Concurrent programming
memory models |
0.8 | 3 | 2017 | Mixed-size concurrency: ARM, POWER, C/C++11, and SC · POPL 2017 Into the depths of C: elaborating the de facto standards · PLDI 2016 An operational semantics for C/C++11 concurrency · OOPSLA 2016 |
Hardware security and side channels
formal verification of security properties |
0.4 | 1 | 2020 | Rigorous engineering for hardware security: Formal modelling and proof in the CHERI design and implementation process · SP 2020 |
Processor architecture and microarchitecture
capability-based architecture |
0.4 | 1 | 2020 | Rigorous engineering for hardware security: Formal modelling and proof in the CHERI design and implementation process · SP 2020 |
Processor architecture and microarchitecture
instruction set architecture |
0.4 | 1 | 2020 | Rigorous engineering for hardware security: Formal modelling and proof in the CHERI design and implementation process · SP 2020 |
Concurrent programming › memory models
weak memory models |
0.3 | 1 | 2017 | Mixed-size concurrency: ARM, POWER, C/C++11, and SC · POPL 2017 |
Programming languages and type systems › language semantics › memory model semantics
c memory model |
0.2 | 1 | 2016 | Into the depths of C: elaborating the de facto standards · PLDI 2016 |
Programming languages and type systems › language semantics
c semantics |
0.2 | 1 | 2016 | Into the depths of C: elaborating the de facto standards · PLDI 2016 |
Programming languages and type systems
language semantics |
0.2 | 1 | 2016 | Into the depths of C: elaborating the de facto standards · PLDI 2016 |
Programming languages and type systems › language semantics › formal semantics
operational semantics |
0.2 | 1 | 2016 | An operational semantics for C/C++11 concurrency · OOPSLA 2016 |
Program verification › formal proof
mechanized proof |
0.1 | 1 | 2020 | Rigorous engineering for hardware security: Formal modelling and proof in the CHERI design and implementation process · SP 2020 |
Concurrent programming › memory models › weak memory models
c11 memory model |
0.1 | 1 | 2017 | Mixed-size concurrency: ARM, POWER, C/C++11, and SC · POPL 2017 |
Software testing
compiler testing |
0.1 | 1 | 2016 | An operational semantics for C/C++11 concurrency · OOPSLA 2016 |
Program analysis › static analysis
pointer analysis |
0.1 | 1 | 2016 | Into the depths of C: elaborating the de facto standards · PLDI 2016 |
Methods — techniques the papers use, named apart from their topics
test generation · 1.3mechanized proof · 1.3formal modeling · 1.3operational semantics · 0.5semantic test cases · 0.2elaboration to core language · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2020 | Rigorous engineering for hardware security: Formal modelling and proof in the CHERI design and implementation processabstractThe root causes of many security vulnerabilities include a pernicious combination of two problems, often regarded as inescapable aspects of computing. First, the protection mechanisms provided by the mainstream processor architecture and C/C++ language abstractions, dating back to the 1970s and before, provide only coarse-grain virtual-memory-based protection. Second, mainstream system engineering relies almost exclusively on test-and-debug methods, with (at best) prose specifications. These methods have historically sufficed commercially for much of the computer industry, but they fail to prevent large numbers of exploitable bugs, and the security problems that this causes are becoming ever more acute.In this paper we show how more rigorous engineering methods can be applied to the development of a new security-enhanced processor architecture, with its accompanying hardware implementation and software stack. We use formal models of the complete instruction-set architecture (ISA) at the heart of the design and engineering process, both in lightweight ways that support and improve normal engineering practice - as documentation, in emulators used as a test oracle for hardware and for running software, and for test generation - and for formal verification. We formalise key intended security properties of the design, and establish that these hold with mechanised proof. This is for the same complete ISA models (complete enough to boot operating systems), without idealisation.We do this for CHERI, an architecture with hardware capabilities that supports fine-grained memory protection and scalable secure compartmentalisation, while offering a smooth adoption path for existing software. CHERI is a maturing research architecture, developed since 2010, with work now underway on an Arm industrial prototype to explore its possible adoption in mass-market commercial processors. The rigorous engineering work described here has been an integral part of its development to date, enabling more rapid and confident experimentation, and boosting confidence in the design. Kyndylan Nienhuis, Alexandre Joannou, Thomas Bauereiß, Anthony C. J. Fox, Michael Roe, Brian Campbell 0001, Matthew Naylor 0002, Robert M. Norton, Simon W. Moore, Peter G. Neumann, Ian Stark, Robert N. M. Watson, Peter Sewell |
SP | 1 |
| 2017 | Mixed-size concurrency: ARM, POWER, C/C++11, and SCabstractPrevious work on the semantics of relaxed shared-memory concurrency has only considered the case in which each load reads the data of exactly one store. In practice, however, multiprocessors support mixed-size accesses, and these are used by systems software and (to some degree) exposed at the C/C++ language level. A semantic foundation for software, therefore, has to address them. Shaked Flur, Susmit Sarkar, Christopher Pulte, Kyndylan Nienhuis, Luc Maranget, Kathryn E. Gray, Ali Sezgin, Mark Batty, Peter Sewell |
POPL | 4 |
| 2016 | An operational semantics for C/C++11 concurrencyabstractThe C/C++11 concurrency model balances two goals: it is relaxed enough to be efficiently implementable and (leaving aside the ``thin-air'' problem) it is strong enough to give useful guarantees to programmers. It is mathematically precise and has been used in verification research and compiler testing. However, the model is expressed in an axiomatic style, as predicates on complete candidate executions. This suffices for computing the set of allowed executions of a small litmus test, but it does not directly support the incremental construction of executions of larger programs. It is also at odds with conventional operational semantics, as used implicitly in the rest of the C/C++ standards. Kyndylan Nienhuis, Kayvan Memarian, Peter Sewell |
OOPSLA | 1 |
| 2016 | Into the depths of C: elaborating the de facto standardsabstractC remains central to our computing infrastructure. It is notionally defined by ISO standards, but in reality the properties of C assumed by systems code and those implemented by compilers have diverged, both from the ISO standards and from each other, and none of these are clearly understood. We make two contributions to help improve this error-prone situation. First, we describe an in-depth analysis of the design space for the semantics of pointers and memory in C as it is used in practice. We articulate many specific questions, build a suite of semantic test cases, gather experimental data from multiple implementations, and survey what C experts believe about the de facto standards. We identify questions where there is a consensus (either following ISO or differing) and where there are conflicts. We apply all this to an experimental C implemented above capability hardware. Second, we describe a formal model, Cerberus, for large parts of C. Cerberus is parameterised on its memory model; it is linkable either with a candidate de facto memory object model, under construction, or with an operational C11 concurrency model; it is defined by elaboration to a much simpler Core language for accessibility, and it is executable as a test oracle on small examples. This should provide a solid basis for discussion of what mainstream C is now: what programmers and analysis tools can assume and what compilers aim to implement. Ultimately we hope it will be a step towards clear, consistent, and accepted semantics for the various use-cases of C. Kayvan Memarian, Justus Matthiesen, James Lingard, Kyndylan Nienhuis, David Chisnall, Robert N. M. Watson, Peter Sewell |
PLDI | 4 |
| 2015 | The Problem of Programming Language Concurrency Semantics
Mark Batty, Kayvan Memarian, Kyndylan Nienhuis, Jean Pichon-Pharabod, Peter Sewell |
ESOP | 3 |