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George Charitopoulos

dblp:160/7742 · also Georgios Charitopoulos · DBLP profile ↗
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4ranked-venue papers
3as first author
1since 2021 · last 2021
0000-0002-7538-5043ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 3 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Reconfigurable computing and FPGAs · 44% Hardware accelerators and domain-specific architectures · 44% Electronic design automation · 13%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs
coarse-grained reconfigurable architecture
0.512021
MC-DeF: Creating Customized CGRAs for Dataflow Applications · ACM Trans. Archit. Code Optim. 2021
Hardware accelerators and domain-specific architectures › spatial architecture
dataflow accelerator
0.512021
MC-DeF: Creating Customized CGRAs for Dataflow Applications · ACM Trans. Archit. Code Optim. 2021
Electronic design automation
design space exploration
0.112021
MC-DeF: Creating Customized CGRAs for Dataflow Applications · ACM Trans. Archit. Code Optim. 2021

Methods — techniques the papers use, named apart from their topics

mapping and routing · 0.5energy and area estimation · 0.5
YearPublicationVenuePosition
2021 MC-DeF: Creating Customized CGRAs for Dataflow Applications
abstract
Executing complex scientific applications on Coarse-Grain Reconfigurable Arrays ( CGRAs ) promises improvements in execution time and/or energy consumption compared to optimized software implementations or even fully customized hardware solutions. Typical CGRA architectures contain of multiple instances of the same compute module that consist of simple and general hardware units such as ALUs, simple processors. However, generality in the cell contents, while convenient for serving a wide variety of applications, penalizes performance and energy efficiency. To that end, a few proposed CGRAs use custom logic tailored to a particular application’s specific characteristics in the compute module. This approach, while much more efficient, restricts the versatility of the array. To date, versatility at hardware speeds is only supported with Field programmable gate arrays (FPGAs), that are reconfigurable at a very fine grain. This work proposes MC-DeF, a novel Mixed-CGRA Definition Framework targeting a Mixed-CGRA architecture that leverages the advantages of CGRAs by utilizing a customized cell array, and those of FPGAs by incorporating a separate LUT array used for adaptability. The framework presented aims to develop a complete CGRA architecture. First, a cell structure and functionality definition phase creates highly customized application/domain specific CGRA cells. Then, mapping and routing phases define the CGRA connectivity and cell-LUT array transactions. Finally, an energy and area estimation phase presents the user with area occupancy and energy consumption estimations of the final design. MC-DeF uses novel algorithms and cost functions driven by user defined metrics, threshold values, and area/energy restrictions. The benefits of our framework, besides creating fast and efficient CGRA designs, include design space exploration capabilities offered to the user. The validity of the presented framework is demonstrated by evaluating and creating CGRA designs of nine applications. Additionally, we provide comparisons of MC-DeF with state-of-the-art related works, and show that MC-DeF offers competitive performance (in terms of internal bandwidth and processing throughput) even compared against much larger designs, and requires fewer physical resources to achieve this level of performance. Finally, MC-DeF is able to better utilize the underlying FPGA fabric and achieves the best efficiency (measured in LUT/GOPs).
George Charitopoulos, Dionisios N. Pnevmatikatos, Georgi Gaydadjiev
ACM Trans. Archit. Code Optim.1
2018 A decoupled access-execute architecture for reconfigurable accelerators
abstract
Mapping computational intensive applications on reconfigurable technology for acceleration requires two main implementation parts: (a) the data plane, i.e., efficient interconnected units that accelerate processing, and (b) the access-plane, i.e., efficient ways to access data and transfer them to/from the accelerator. Data plane construction is well understood and mature tools -such as High Level Synthesis (HLS)- that produce efficient reconfigurable architectures exist. The access plane, however, is more challenging: data fetching for big-data and high-performance computing applications is even more complex and time consuming than processing.
George Charitopoulos, Charalampos Vatsolakis, Grigorios Chrysos 0001, Dionisios N. Pnevmatikatos
CF1
2017 Run-time management of systems with partially reconfigurable FPGAs
George Charitopoulos, Iosif Koidis, Kyprianos Papademetriou, Dionisios N. Pnevmatikatos
Integr.1
2016 mCluster: A Software Framework for Portable Device-Based Volunteer Computing
abstract
Recent market forecasts predict that the portable computing trend will vastly spread, as by 2020 there will bemore than 3 billion LTE device users worldwide. Motivated by this fact, many companies and research institutes have already launched research projects that utilize portable devices, voluntarily provided by users, to perform the required computations. Many such projects employ Berkeley's BOINC middleware, since it can support a large variety of stationary and mobile devices. However, currently available BOINC high-level APIs, either do not support portable devices or lack advanced processing capabilities (such as inter-node task dependencies) and/or easiness of use. To resolve these issues, we propose the mCluster software framework for application execution powered by the BOINC middleware on portable devices. mCluster adopts a task-based programming model that requires simple, pragma-based annotations of the application software, in order to dynamically resolve task dependencies. To evaluate our framework, we have have mapped a scientific application from the neuroscience domain on an small-scaled network of portable devices. mCluster significantly reduces the required programming effort and complexity to efficiently map BOINC-powered applications with task dependencies on portable devices compared to previous approaches.
Dimitris Theodoropoulos 0001, Grigorios Chrysos 0001, Iosif Koidis, George Charitopoulos, Emmanouil Pissadakis, Antonis Varikos, Dionisios N. Pnevmatikatos, Georgios Smaragdos, Christos Strydis, Nikolaos A. Zervos
CCGrid4