Boolean satisfiability (SAT) solving is a foundational problem in computer science and serves as a core engine for a wide range of combinatorial optimization tasks. It underpins critical applications across formal verification, electronic design automation (EDA), artificial intelligence (AI) reasoning, crypt-analysis, bioinformatics, and constraint programming. While significant progress has been made in algorithmic improvements, these advances are gradually reaching saturation, motivating increasing attention toward domain-specific hardware accelerators beyond the von Neumann architecture. However, existing hardware SAT accelerators often face significant deployment barriers due to reliance on pseudo-random number (PN) generators, specialized analog components with sufficient intrinsic noise, or unconventional fabrication technologies such as memristors. These limitations hinder scalability, portability, and integration into mainstream digital design flows. This paper presents an intrinsically stochastic, fully digital SAT accelerator inspired by analog mixed-signal crossbar architectures. The proposed design eliminates the need for analog noise sources, PN generators, or true-random number (TN) generators, enabling a fully synthesizable, standard-cell-based implementation compatible with conventional digital flows. Digital counters are employed as “spins”, acting as oscillatory elements that store and flip variable states, thus supporting robust and scalable stochastic behavior. Stochasticity is achieved through a novel polynomial clause-to-variable feedback mechanism, which dynamically modulates oscillator frequencies based on clause satisfaction states, allowing effective exploration of the solution space without external randomness. A highly parallel crossbar structure further accelerates problem-solving by enabling concurrent evaluation of multiple clauses, aided by a proposed polynomial clause-to-variable feedback function. To validate the proposed architecture, we implemented prototypes on FPGA and three ASIC platforms including 12 nm FinFET, 22 nm and 65 nm CMOS technologies. The designs were evaluated on a suite of hard SAT benchmark problems with 20 to 250 variables. Our 22nm ASIC accelerator achieves an approximately$3.06 \times$speedup than the state-of-the-art 28 nm 3-SAT accelerator. Compared with prior 65 nm designs, ours achieves 100% solvability with comparable runtime. Notably, we present the first 3-SAT accelerator capable of handling 250 variables with 100% solvability, marking a significant advancement in scalability for digital SAT accelerators.

Analog mixed-signal (AMS) circuit architecture has evolved towards more digital friendly due to technology scaling and demand for higher flexibility/reconfigurability. Mean-while, the design complexity and cost of AMS circuits has substantially increased due to the necessity of optimizing the circuit sizing, layout, and verification of a complex AMS circuit. On the other hand, machine learning (ML) algorithms have been under exponential growth over the past decade and actively exploited by the electronic design automation (EDA) community. This paper will identify the opportunities and challenges brought about by this trend and overview several emerging AMS design methodologies that are enabled by the recent evolution of AMS circuit architectures and machine learning algorithms. Specifically, we will focus on using neural-network-based surrogate models to expedite the circuit design parameter search and layout iterations. Lastly, we will demonstrate the rapid synthesis of several AMS circuit examples from specification to silicon prototype, with significantly reduced human intervention.

A digital finite impulse response (FIR) filter design is fully synthesizable, thanks to the mature CAD support of digital circuitry. On the contrary, analog mixed-signal (AMS) filter design is mostly a manual process, including architecture selection, schematic design, and layout. This work presents a systematic design methodology to automate AMS FIR filter design using a time approximation architecture without any tunable passive component, such as switched capacitor or resistor. It not only enhances the flexibility of the filter but also facilitates design automation with reduced analog complexity. The proposed design flow features a hybrid approximation scheme that automatically optimize the filter's impulse response in light of time quantization effects, which shows significant performance improvement with minimum designer's efforts in the loop. Additionally, a layout-aware regression model based on an artificial neural network (ANN), in combination with gradient-based search algorithm, is used to automate and expedite the filter design. With the proposed framework, we demonstrate rapid synthesis of AMS FIR filters in 65nm process from specification to layout.

Stochastic time-to-digital converters (STDCs) are gaining increasing interest in submicron CMOS analog/mixed-signal design for their superior tolerance to nonlinear quantization levels. However, the large number of required delay units and time comparators for conventional STDC operation incurs excessive implementation costs. This paper presents a fully synthesizable STDC architecture based on an integral non-linearity (INL) scrambling technique, allowing order-of-magnitude cost reduction. The proposed technique randomizes and averages the STDC INL using a digital-to-time converter. Moreover, we propose an associated design automation flow and demonstrate an STDC design in 12nm FinFET process. Post-layout simulations show significant linearity and area/power efficiency improvements compared to prior arts.

Among different types of regression methods to model Analog/Mixed-Signal (AMS) circuits, the Artificial Neural Network (ANN) is a promising candidate due to its reasonable accuracy and fast evaluation. However, for complex AMS circuits with wide specification ranges, creating an ANN model requires a large training dataset. To reduce the required training dataset’s volume, we have proposed a circuit-connectivity-inspired ANN (CCI-NN), including multiple sub-ANNs linked according to the actual circuit connections. For validation, we have employed CCI-NN to model a three-stage amplifier and a current-steering digital-to-analog converter. For a certain modeling accuracy, the training dataset requirement is reduced by 3.5x-7.6x.

We propose a complete analog mixed-signal circuit design flow from specification to silicon with minimum human-in-the-loop interaction, and verify the flow in a 12nm FinFET CMOS process. The flow consists of three key elements: neural network (NN) modeling of the parameterized circuit component, a search algorithm based on NN models to determine its sizing, and layout automation. To reduce the required training data for NN model creation, we utilize transfer learning to improve the NN accuracy from a relatively small amount of post-layout/silicon data. To prove the concept, we use a voltage-controlled oscillator (VCO) as a test vehicle and demonstrate that our design methodology can accurately model the circuit and generate designs with a wide range of specifications. We show that circuit sizing based on the transfer learned NN model from silicon measurement data yields the most accurate results.

A traditional analog mixed-signal (AMS) design mostly relies on the designer's knowledge and can only afford exploring over a narrow design space due to expensive SPICE simulation. However, a neural network (NN)-based model of an AMS circuit potentially enables fast exploration of the design space thanks to its low computation cost. Unfortunately, to build an NN model with sufficient accuracy, a training dataset is needed, incurring SPICE simulations during different design phases. Therefore, it is prudent to train it with a larger dataset in an earlier design phase (e.g. schematic design) but a significantly reduced dataset in a later design phase (e.g. postlayout design or migration to more advanced technology node), as simulation cost increases sharply in later design phases. In this paper, we propose the use of transfer learning (TL) with Bayesian optimization-aided sampling (BOAS) to reduce the required size of training datasets for NN models in later design phases. To prove the concept, we show that 150X and 17X dataset reductions are possible for a digital-to-analog converter (DAC) in the post-layout design phase and an amplifier in the technology migration phase, respectively.

The design and verification of analog and mixed-signal (AMS) circuits typically involve many time-consuming simulations to qualify target specifications or optimize the design parameters for better performance. The long simulation time significantly slows down the speed of optimization iterations for both human designers and automatic AMS optimizers, inevitably resulting in high design costs and less-optimized designs. In this work, we propose a convolutional neural network (CNN)-based early performance assertion (CEPA) scheme to identify designs with unsatisfactory performance quickly and accurately. Thanks to the feature extraction capability of CNN, CEPA only requires a short duration of transient waveform to predict the satisfaction of the target specifications for a certain design that is otherwise obtained by a long transient simulation. In addition, applying the fine-tuning technique to the proposed CEPA scheme can further extend the inference from schematic-level simulation to post-layout simulation with only a few training samples (i.e., enhancing CEPA's usage with a low training cost). A sample-and-hold circuit and a delta-sigma digital-to-analog converter are presented to prove the effectiveness of the proposed CEPA scheme. With its maximum assertion accuracy of 99%, CEPA reduces the simulation time for assertion by orders of magnitude.