Neuromorphic TinyML (vTinyML) aims at solving problems in machine perception and intelligence at the edge that necessitate low latency processing, using low resource processors that have neuromorphic event-based sensory interfaces and neuromorphic accelerators. In this paper, we report on a neuromorphic TinyML architecture (vMCU) which can be leveraged to be deployed to process data from event-based sensors on the edge. The core of the system is a RISC-V CPU from SiFive which is used for algorithm development. The CPU interfaces with a set of communication and computation peripherals which are comprised most notably of an event-based physical interface which has a 256Kib FIFO, a programmable 47-bit time-stamping unit and an embedded Compute in Memory (CiM) associative processor employing charge based processing and a pseudo-DRAM cell primitive. The vMCU SOC was fabricated in 65nm CMOS, has a die size of$7\text{mm}\times 4\text{mm}$, runs at 100MHz and has a maximum event throughput at its physical interface of 17Meps. Binary and integer operations on long bit vectors using the CiM accelerator capabilities take a few fJ per Op. vMCU capability consumes 30mW and is demonstrated in various tasks for embedded applications, including character recognition from a DAVIS240C event-based camera.

Mining engineering metaknowledge from electronic documents is important in devising new design solutions for emerging applications as well as in identifying new business opportunities. Continuously and comprehensively reviewing and assessing the entire technical literature to find the most relevant ideas and solutions is cumbersome as engineering innovations are constantly being proposed. In particular, high performance analog circuit design has been at the forefront of technological innovations given their importance in applications, like telecommunications, mobile applications, and health care. This paper proposes a model and mining techniques for representing analog circuit design metaknowledge. The metaknowledge representation includes three components: an associative component presenting the conceptual hierarchy of the considered circuits, a component expressing the performance capabilities (e.g., tradeoffs and bottlenecks) of the circuits, and a causal modeling part describing the more likely starting ideas and design plans used to create a circuit. Knowledge structures can be used to tackle new applications, identify opportunities to improve existing circuits, and validate design correctness. A case study illustrates the proposed knowledge structure for a set of 30 modern, high-frequency analog circuits.