The execution of deep neural network (DNN) algorithms suffers from significant bottlenecks due to the separation of the processing and memory units in traditional computer systems. Emerging memristive computing systems introduce an in situ approach that overcomes this bottleneck. The nonvolatility of memristive devices, however, may expose the DNN weights stored in memristive crossbars to potential theft attacks. Therefore, this article proposes a 2-D permutation-based protection (TDPP) method that thwarts such attacks. We first introduce the underlying concept that motivates the TDPP method: permuting both the rows and columns of the DNN weight matrices. This contrasts with previous methods, which focused solely on permuting a single dimension of the weight matrices, either the rows or columns. While it is possible for an adversary to access the matrix values, the original arrangement of rows and columns in the matrices remains concealed. As a result, the extracted DNN model from the accessed matrix values would fail to operate correctly. We consider two different memristive computing systems (designed for layer-by-layer and layer-parallel processing, respectively), and demonstrate the design of the TDPP method that could be embedded into the two systems. Finally, we present a security analysis. Our experiments demonstrate that TDPP can achieve comparable effectiveness to prior approaches, with a high level of security when appropriately parameterized. In addition, TDPP is more scalable than previous methods and results in reduced area and power overheads. The area and power are reduced by, respectively,$1218\times $and$2815\times $for the layer-by-layer system and by$178\times $and$203\times $for the layer-parallel system compared to prior works.

Neural networks (NN) have gained great success in visual object recognition and natural language processing, but this kind of data-intensive applications requires huge data movements between computing units and memory. Emerging resistive random-access memory (RRAM) computing systems have demonstrated great potential in avoiding the huge data movements by performing matrix-vector-multiplications in memory. However, the nonvolatility of the RRAM devices may lead to potential stealing of the NN weights stored in crossbars and the adversary could extract the NN models from the stolen weights. This paper proposes an effective security enhancing method for RRAM computing systems to thwart this sort of piracy attack. We first analyze the theft methods of the NN weights. Then we propose an efficient security enhancing technique based on obfuscating the row connections between positive crossbars and their pairing negative crossbars. Two heuristic techniques are also presented to optimize the hardware overhead of the obfuscation module. Compared with existing NN security work, our method eliminates the additional RRAM writing operations used for encryption/decryption, without shortening the lifetime of RRAM computing systems. The experiment results show that the proposed methods ensure the trial times of brute-force attack are more than (16!)17and the classification accuracy of the incorrectly extracted NN models is less than 20%, with minimal area overhead.

Due to the globalization trend of IC industry, more and more chips are designed and/or fabricated by foreign companies and foundries. Among all the consequences of this globalization trend, the possible existence of stealthy-inserted hardware Trojans (HTs) has raised a great security concern. Without the awareness of the end users or the original designers of host circuits, HTs are usually inserted stealthily at one of the outsourced design or fabrication stages, remain (almost) harmless to the host on dormant mode, and upon triggered will disturb the functions and/or leak the secrets carried by the host. It could become a serious security leak of the systems built on top of infected chips. Identifying whether a circuit carries an HT is thus of the utmost importance to mission-critical applications. Speaking from the point of HT designers, nets with extreme state probabilities could be used to create rare state combination for the purpose of HT triggering. Besides, HT designers seek nets with low switching probabilities to insert their HTs in order not to increase power leakage. We denote the nets with extreme state probability as extreme nets and the nets with low switching probability as inactive nets. It is commonly believed that in order to minimize the chance of accidental triggering or power analysis, they would be better to choose, among all the nets of the host, the nets that with extreme state probabilities (extreme nets) or the nets that barely switch (inactive nets) to construct the trigger parts of their HTs, respectively. However, a net of a circuit experiences very different state probabilities and switching probabilities on test mode and function mode, and existing works have only considered the former. The nets with low activeness on both test mode and function mode hence will be the “best candidates.” In this paper we will first build the ground on finding the nets with low activeness on function mode, and then propose a fast heuristic method approach. The method runs in minimal complexity, has high accuracy, and is tested on popular benchmarks and large-sized circuits.