Demo Data from EDBT 2026 / reviewers in the wild / expert
Ali Fakhrzadehgan
dblp:161/0805
· DBLP profile ↗
3ranked-venue papers
2as first author
2since 2021 · last 2023
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 2 first-author · 2 since 2021Security and privacy · 1 · 1 first-author · 1 since 2021Software engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 81% Hardware reliability and fault tolerance · 19% | |
| Network and information security
1 paper |
Authentication and access control · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Authentication and access control › access control
integrity protection |
0.6 | 1 | 2022 | SafeGuard: Reducing the Security Risk from Row-Hammer via Low-Cost Integrity Protection · HPCA 2022 |
Memory systems › DRAM
rowhammer |
0.6 | 1 | 2022 | SafeGuard: Reducing the Security Risk from Row-Hammer via Low-Cost Integrity Protection · HPCA 2022 |
Memory systems
DRAM |
0.2 | 1 | 2022 | SafeGuard: Reducing the Security Risk from Row-Hammer via Low-Cost Integrity Protection · HPCA 2022 |
Hardware reliability and fault tolerance › error correction
error-correcting codes |
0.2 | 1 | 2022 | SafeGuard: Reducing the Security Risk from Row-Hammer via Low-Cost Integrity Protection · HPCA 2022 |
Methods — techniques the papers use, named apart from their topics
MAC · 1.1ECC reorganization · 1.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2023 | SecDDR: Enabling Low-Cost Secure Memories by Protecting the DDR InterfaceabstractThe security goals of cloud providers and users include memory confidentiality and integrity, which requires implementing replay attack protection (RAP). RAP can be achieved using integrity trees or mutually authenticated channels. Integrity trees incur significant performance overheads and are impractical for protecting large memories. Mutually authenticated channels have been proposed only for packetized memory interfaces that address only a very small niche domain, require fundamental changes to memory system architecture, and assume fully-trusted modules. We propose SecDDR, a low-cost RAP that targets direct-attached memories, like DDRx. SecDDR avoids memory-side data authentication, and thus, only adds a small amount of logic to memory components and does not change the underlying DDR protocol, making it practical for widespread adoption. In contrast to prior mutual authentication proposals, which require trusting the entire memory module, SecDDR targets untrusted modules by placing its limited security logic on the DRAM die (or package) of the ECC chip. Our evaluation shows that SecDDR performs within 1% of an encryption-only memory without RAP and that SecDDR provides 18.8% and 7.8% average performance improvements (up to 190.4% and 24.8%) relative to a 64-ary integrity tree and an authenticated channel, respectively. Ali Fakhrzadehgan, Prakash Ramrakhyani, Moinuddin K. Qureshi, Mattan Erez |
DSN | 1 |
| 2022 | SafeGuard: Reducing the Security Risk from Row-Hammer via Low-Cost Integrity ProtectionabstractRow-Hammer (RH) is a DRAM data-disturbance failure that occurs when a row is activated frequently, which causes bit-flips in nearby rows. Row-Hammer is a significant security threat as an attacker can exploit the bit-flips to do privilege escalation and leak confidential data. While several solutions aim to mitigate RH, such solutions depend on the RH threshold and adversarial access patterns. Solutions developed for a given threshold become ineffective for newer devices with lower thresholds, and new attack patterns continue to break existing mitigations. Currently, there is no guaranteed solution for RH, which means that the system remains vulnerable to security threats even in the presence of RH mitigation.In this paper, we contend that simply relying on RH mitigation is insufficient to provide security in the presence of reducing threshold and motivated attackers. We propose SafeGuard, which equips the system with low-cost integrity protection as a defense against potential attacks that break the RH mitigation. As SafeGuard can detect arbitrary failures, it converts the problem of RH bit-flips from a security threat (silent consumption of corrupted data) to a reliability concern (detectable uncorrectable errors caused by integrity violation). We develop SafeGuard for systems that employ ECC modules and show that SafeGuard can provide strong detection to both SECDED (46-bit MAC per cache-line) and Chipkill (32-bit MAC per cache-line) while retaining the correction capability of conventional designs. SafeGuard avoids incurring any storage overheads in DRAM by simply reorganizing the ECC code to operate at a cache-line granularity (64 bytes) instead of a word granularity (8 bytes). Our evaluations show that SafeGuard has a negligible impact on both the system performance (0.7%) and the system reliability due to naturally occurring errors while still providing a strong defense against the security risk of RH by detecting arbitrary bit-flips. Ali Fakhrzadehgan, Yale N. Patt, Prashant J. Nair, Moinuddin K. Qureshi |
HPCA | 1 |
| 2015 | An energy-efficient virtual channel power-gating mechanism for on-chip networks
Amirhossein Mirhosseini, Mohammad Sadrosadati, Ali Fakhrzadehgan, Mehdi Modarressi, Hamid Sarbazi-Azad |
DATE | 3 |