This article presents an algorithm for integrated timing-driven latch placement and cloning. Given a circuit placement, the proposed algorithm relocates some latches while circuit timing is improved. Some latches are replicated to further improve the timing; the number of replicated latches along with their locations are automatically determined. After latch cloning, each of the replicated latches is set to drive a subset of the fanouts that have been driven by the original single latch. The proposed algorithm is then extended such that relocation and cloning are applied to some latches together with their neighbor logic gates. Experimental results demonstrate that the worst negative slack and the total negative slack are improved by 24% and 59%, respectively, on average of test circuits. The negative impacts on circuit area and power consumption are both marginal, at 0.7% and 1.9% respectively.

Modern standard cells contain intercell margins at the left and right ends for better lithography. We introduce defect probability, which is the probability that a lithography defect occurs if the margins between two adjacent cells are missing. Computing the defect probability of all cell pairs is impractical due to lengthy lithography simulations and huge number of cell pair combinations. Two approximate methods are employed to make this computation possible: reducing the range of optical proximity correction and grouping cell pairs of similar geometry at the cell boundary. We also present how the cell layout can be modified for a lower defect probability with no impact on the cell electrical parameters. Defect probability is applied to two physical design optimization problems. In the automatic placement, we consider that all cells are initially without margins. We want to locate two cells adjacent if their defect probability is zero (or negligibly small) or insert margins in between; this is achieved using the average defect probability as one of the cost terms of the placement. Experiments in 28-nm commercial library demonstrate an 8% reduction in the area with a 4% shorter wirelength. In the second application, we assume that the standard placement using cells with margins have been performed. We want to identify redundant margins that can be removed while the defect probability is kept zero. We take a step forward and shuffle the location of a few consecutive cells in the same row so that more redundant margins are identified. Once all the redundant margins are removed, newly created whitespace is distributed to reduce routing congestion in highly congested areas. Experiments indicate a 48% reduction in the number of overflow routing grids.

In sub-7nm technology, the size and pitch of vias are much smaller than optical resolution limit, and directed self-assembly lithography with multiple patterning technology (MP-DSAL) has been proposed as a solution. In MP-DSAL, vias that are close are clustered and patterned together via DSAL process, and via clusters that are close are printed using different masks via MP. Redundant vias, which are typically used for better via manufacturability, should be inserted very carefully in MP-DSAL because some redundant vias may cause large and complex via clusters, which are undesirable in DSAL; some other redundant vias may cause mask assignment of via clusters impossible, often called MP coloring conflict.

In directed self-assembly lithography (DSAL), an inter-cell cluster of contacts, which crosses the boundary of cells, is more likely to cause patterning failure because corresponding guide pattern (GP) has not been verified beforehand. All forms of inter-cell clusters can systematically be identified and grouped, which allows us to define DSA defect probability when two arbitrary cells are placed side by side. We then address post-placement optimization, in which some cells are flipped and some cells are swapped with their adjacent cells so that the number of whitespaces inserted in between cell pairs of high defect probability is minimized. Experiments with a few test circuits demonstrate 11% increase of placement density, on average, with no expected DSA defects.