This paper presents a generalized and simplified theoretical framework for the analysis of a variety of two-port linear, periodically time-variant (LPTV) true-time-delay (TTD) lines. The analysis is done almost entirely in the time domain using impulse response. The two-port analysis is split into two different phases of operation, each modeled as an LTI operation; one in the sampled domain and the other in the continuous-time domain. In the first phase (step 1), the approach leverages adjoint-network analysis to find the impulse response (and by extension, the transfer function) between the input and the samples on the N-path capacitors. This simplifies the analysis, while establishing an LTI relationship between the input and the samples. In the second phase of the analysis the continuous-time voltage through the output port is evaluated. Recognizing that the samples on the N-path capacitors act as the input for the continuous-time output through the output port, this analysis (step 2) is shown to reduce to another LTI operation. Unlike conventional kernel-based methods, the framework can readily handle N-path two-port architectures while incorporating the effect of non-idealities, like non-zero on-resistance of the switches, and non-zero capacitors at the two ports without introducing additional analytical complexity. An extension of the methodology is also shown to accurately analyze the frequency response if there is an overlap between the clocks connecting the ports and also to evaluate the input impedance of the two-port delay-line accurately. The analytical expressions derived through this framework is shown to have excellent agreement with circuit-level simulations.

This work presents a programmable, linear, periodically time-variant (LPTV) bandpass true-time-delay line which does not require a dedicated tunable clock-phase delay generator. The architecture provides true-delays, which are independent of the time-period of the clock to passband signals, and out-of-band (OOB) blocker attenuation due to its bandpass nature. It operates by embedding a programmable order linear-time-invariant (LTI) delay-line within the switches of an N-path structure, thus translating the low-frequency delay to the RF. Simulation results point to a realizable programmable delay between 3-6 ns for center frequencies between 1-5 GHz over an RF bandwidth of 100 MHz.

Low voltage class-AB operational amplifiers which need to drive large loads, for low-frequency applications require signal coupling between the gates of the push-pull transistors. When realized through a coupling capacitor, this scheme requires a large bias setting resistor to ensure extremely low corner frequency of operation. In the presence of gate leakage, the voltage drop across the large resistor often makes this topology unusable in the modern leakage-prone technology nodes. In this work, we introduce an automatic leakage compensation mechanism that makes the use of capacitively-coupled class-AB stage feasible even in the presence of non-negligible gate-leakage.

An analysis of the inherent trade-offs of the existing feed-forward architectures for wideband applications is presented. A current-reused, class-AB, feed-forward compensated operational amplifier (opamp) capable of driving large capacitive loads is proposed. The architecture is based on sharing a single output stage between the gain and the compensation paths using AC-coupling between them, while retaining the inherent class-AB operation of the output stage. The bandwidth of the opamp is enhanced by boosting the transconductance of the compensation path using a pre-amplifier. The opamp is shown to support a load capacitance of 10 pF while maintaining >40 dB baseband gain over a frequency range of 100 MHz while maintaining a phase-margin in excess of 60° in a standard 65 nm bulk-CMOS technology.

A unique property of two-path filter is exploited to reject close-in blocker bands near a desired receiver band. It is based on the observation that each path in a two-path filter averages one half-cycle of the input carrier. If the carrier and the filter's clocks have same frequencies, the average over half-cycle of a sinusoid depends on the phase difference between the clock and the input. A 90oor 270ophase difference can result in a zero average, and potentially a perfect carrier suppression. Since this principle of blocker suppression is based on a relative phase relationship between the clock and the blocker, and not a relative frequency separation between the bands, it is shown to break the trade-offs plaguing the pass-band width of a filter and the extent of close-in blocker suppression. A digitally auto-tuned loop that calibrates the 2-path clocks to the desired phase is proposed. The proposed two-path architecture is shown to attenuate close- in blockers more efficiently than the traditional bandpass and bandstop N-path filters.

The distortion performance of two-stage Miller and feed-forward operational amplifiers (opamps) under negative feedback are studied, and their inter-modulation strengths near the band-edge compared analytically. Recognizing that distortion increases with frequency, intuitive analytical models to estimate distortion near the band-edge of the closed loop system are developed. It is established that feed-forward configuration is fundamentally more linear than its Miller counterpart at the band-edge of the closed loop system, where the loop gain of both the topologies are identical.

A wideband, gain enhanced, high frequency, fully differential operational transconductance amplifier (OTA) with enhanced linearity is proposed. The OTA uses a negative conductance to cancel its output parasitic conductance. An automatic, digitally controlled, feedback tuning loop ensures that the parasitic conductance is tracked across corners. High linearity is achieved by voltage biasing the transistors and allowing higher headroom. The OTA uses a common mode feedback (CMFB) loop for common mode stabilization instead of diode connected transistors which enhances the achievable bandwidth. Simulations in a standard 130 nm CMOS process show a dc gain enhancement from 14 dB to 42 dB when negative conductance in incorporated across process voltage and temperature (PVT). The OTA has an unity gain bandwidth of 20 GHz. It has an input referred noise of 1.75 nV/√(Hz) and has -40dB total harmonic distortion for an input of 330 mVppd.

An enhanced gain, high frequency, operational transconductance amplifier (OTA) architecture using negative conductance load to cancel its output parasitic conductance across process, voltage, and temperature (PVT) variations without the need of any off-chip intervention is proposed. Simulation results of a prototype transconductor in 0.13μm CMOS process over process corners, 100°C temperature range, and ±10% supply voltage variations show that the DC gain is enhanced from 14dB to 48dB when cancellation using negative conductance is incorporated. A minimum DC gain of 34dB and an average DC gain of 46dB is observed over 500 Monte-Carlo mismatch runs. The OTA has a unity gain bandwidth (UGB) of 20GHz.