Increasing complexity in power management (PMT) has led to a growing demand for third-party power managers (3PPMs) in Network-on-Chip based Mixed-Critical Systems (NoCMCS). However, a malicious 3PPM can exploit the interdependence of power amongst the router nodes to orchestrate well-structured, covert power attacks. Detection and localization of a malicious 3PPM is crucial to restore standard dynamic PMT and mitigating system performance degradation. We propose a novel, non-invasive, low-overhead, attack detection and localization framework for Hardware Trojan (HT)-assisted intermittent power attacks with random activation and deactivation phases in NoCMCS. In Phase-I, our framework makes use of pre-profiled thermal statistics of router nodes to detect any anomaly at runtime. In Phase-II, it leverages a self-aware methodology to locate the router nodes with malicious 3PPM. The proposed framework can detect multiple intermittent HTs in the network. Experimental evaluations on real-life benchmarks show that Phase-I of our framework is able to consolidate the search space of malicious nodes, reducing almost 90% of Phase-II’s computational workload. Phase-II localizes the malicious router nodes across various experimental scenarios with zero false positives. We also demonstrate the robustness of our framework for detecting and localizing malicious router nodes for different intermittent HTs with varying burst attacks over time.

Modern Multi-Processor-Systems-on-Chips (MPSoCs) use Network-on-Chips (NoCs) as a scalable and efficient communication fabric. The applications running on these devices rely on frequent communication with central database servers, which are vulnerable to impersonation attacks by adversarial clones. We propose NoCiPUF, a novel NoC-based intrinsic Physically-Unclonable-Function (PUF) framework for MPSoCs authentication. We re-use the circuit switched nature of NoC with path-pairs as challenges to obtain secret responses, collectively called challenge-response-pairs (CRPs). Due to the random nature of manufacturing variations, equal hop paths exhibit unequal delays. We leverage the delay differences of flits traversing in equal-hop paths to generate unique responses. NoCiPUF is fully-synthesizable and readily scalable as it requires changes only at the behavioral level. To counter Machine-Learning (ML)-based modeling attacks on PUFs, we provide a comprehensive technique and reduce the prediction accuracy to ~52%. NoCiPUF framework incurs low area (0.76%) and power (1.14%) overheads and has no impact on NoC performance in normal mode due to independent authentication mode. Obtained responses have near-ideal PUF metrics and are verified against the NIST randomness test suite. This scheme offers high number of CRPs in larger NoC networks ($>0.74$million CRPs in 5×5 mesh), proving its scalability.

Wireless Network-on-Chip (WNoC) requires a Medium Access Control (MAC) mechanism for an interference-free sharing of the wireless channel. In traditional MAC, a token is circulated among the Wireless Interfaces (WIs) in a Round Robin manner. The WI with the token holds the channel for a fixed number of cycles. However, the channel requirement of the individual WIs dynamically changes over time due to the varying traffic density across the WNoC. Moreover, the conventional WNoCs give equal importance to all the traffic taking the wireless path and transmit it in an oldest-first manner. Nevertheless, the critical data can degrade the system performance to a large extent by delaying the application runtime if not served promptly. We propose 2DMAC, which can change the token arbitration pattern and tune the channel hold time of each WI based on its runtime traffic density and criticality status. Moreover, 2DMAC prioritizes the critical traffic over the non-critical traffic during the wireless data transfer. The proposed mechanism improves the wireless channel utilization by 15.67% and the network throughput by 29.83% and reduces the critical data latency by 29.77% over the traditional MAC.

The contemporary Network on Chips (NoCs) are becoming intricate in design to serve the high throughput and low latency demands of multicore platforms. The complexity level of interconnect module makes it extremely difficult to ensure the functional correctness at the presilicon verification stage. Hence, post-silicon debug is performed on NoC as a necessary step to capture the escaped network design faults. The traditional store and forward trace-based debug methods encounter the problems of large trace buffer requirement and limited availability of trace communication bandwidth. These constraints become more stringent for short-lived network faults (misroute, packet drop, etc.), which demand more frequent trace collection for their detection. In this regard, we propose WiND, which is wireless-enabled NoC for post-silicon debug. WiND is a robust NoC debug framework that optimally uses the limited trace buffer space and can efficiently speed up the trace communication. The proposed method augments wireless interfaces (WIs) on top of the baseline wired NoC for validation purposes. The wireless medium is utilized for long-range test payload communication to reduce the volume of trace. The WIs are also used for high-speed interchip trace transfer. A modified router architecture is used to enable the trace collection, and to enhance the trace communication. WiND platform is examined with several synthetic and SPLASH-2 benchmark workloads, and compared with the traditional wired platform. An overall improvement of 15%–26% on fault detection and 27%–34% on path reconstruction in the case of different faults is observed for the same trace buffer size.

The contemporary network-on-chips (NoCs) are so complex that capturing all network functional faults at presilicon verification stage is nearly impossible. So, on-chip design-for-debug (DfD) structures such as trace buffers are provided to assist capturing escaped faults during post-silicon debug. Most of the DfD modules are left idle after the debug process. Reuse of such structures can compensate for the area overhead introduced by them. In this work, the trace buffers are reutilized as extended virtual channels for the router nodes of an NoC during in-field execution. Optimal distribution of trace buffers among the routers is performed based upon their load profiling. Experiments with several benchmarks on the proposed architecture show an average of 11.36% increase in network throughput and 13.97% decrease in average delay.

Wireless Network-on-Chip (WNoC) broadly adopts single channel for low overhead data transmission. Sharing of the channel among multiple wireless interfaces (WIs) is controlled by a channel access mechanism (CAM). Such CAM can be malfunctioned by a Hardware Trojan (HT) in a malicious WI or a rogue third party intellectual property (IP) core present on the same System-on-Chip (SoC). This may result in denial-of-service (DoS) or spoofing in WNoC leading to starvation of healthy WIs and under-utilization of wireless channel. Our work demonstrates possible threat model on CAM and proposes low overhead decentralized countermeasures for both DoS and spoofing attacks in WNoC.

Wireless Network-on-Chip (WNoC) has been proposed to overcome long-distance communication bottlenecks of wired NoCs. Token passing mechanism has generally been adapted to allocate the wireless channel among Wireless Interfaces (WIs). In this work, we propose a comparator based controller to provide a flexible and efficient channel allocation scheme. It utilizes a comparator attached to the antenna, along with modifications to header flit to perform channel allocation along with power gating WIs to save energy. Evaluation of proposed scheme on CPU/GPU system shows 53% reduction in token passes and 9% energy saving as compared to timer based approach.

Long range, low latency wireless links in Networks-on-Chip (NoCs) have been shown to be the most promising solution to provide high performance intra/inter-chip communication in many core era. Significant advancements have been made in design of both Wireless NoC (WNoC) topologies and transceiver circuits to support wireless communication at chip level. However, a comprehensive understanding of wireless physical layer and its impact on performance is still lacking. There is still a lot of scope for thorough analysis of the affects of intra-chip wireless channel and antenna characteristics on signal transmission and link reliability in WNoCs. To this end, we analyse signal propagation through wireless channel by accurately modelling the intra-chip environment. We analyse the effects of antenna placement across chip plane and its directionality on the signal loss, delay and dispersion properties. The analysis shows that directional antenna exhibits better delay characteristics, while omnidirectional antennas have low loss for signal transmission in the channel. Furthermore, the placement of antenna shows considerable impact on channel characteristics due to reflections from chip edges and constructive or destructive interference between the multiple signal components. This work provides crucial insights into propagation characteristics of on-chip wireless links for better design of transceiver components and their performance.