This work introduces the Split-Posit format, designed to mimic the benefits of high-precision Posit values at significantly lower bit widths, achieving a favourable trade-off between accuracy and hardware efficiency. Furthermore, we propose a specialized digital signal processing (DSP) architecture for embedded FPGAs tailored for Split-Posit arithmetic, efficient and well-suited for its variable-length field structure.

Montgomery Modular Multiplication (MMM) is one of the most widely employed modules in cryptographic hardware due to its ability to avoid costly division operations during modular reduction. In this work, an efficient Montgomery modular multiplication architecture based on the Overlap-Free Karatsuba Algorithm (OKA) is proposed in this work. The OKA technique restructures the multiplication process by eliminating overlapping terms and thereby reduces the critical-path delay. Furthermore, optimized evaluation and interpolation matrices are employed to simplify arithmetic operations and eliminate subtraction operations. OKA lower multiplier has been used to compute modulo operation without doing full multiplication. The proposed architecture demonstrates significant improvements in operational efficiency when implemented on the Virtex-7 FPGA board. Experimental results indicate that the proposed design achieves latency reductions of approximately 53.78%, 52.05%, 52.164%, 47.45%, 44.231% and 46.222% for operand sizes of 32, 64, 128, 256, 512 and 1024 bits respectively, when compared with existing state-of-the-art (SOTA) implementations. The proposed design also achieves significant area reduction of approximately 20.33%, 27.231%, 16.89%, 13.191%, 16.31% and 40.695% for the corresponding operand sizes. In addition to the latency and area improvements, the proposed design also achieves considerable power savings of about 27.33%, 46.712%, 31.724%, 55.93%, 29.32% and 43.664% for the corresponding operand sizes. Similar performance trends are observed in the ASIC implementation results which was obtained using the OpenROAD design flow with the Nangate45 standard cell library.

Biomedical diagnostic platforms increasingly require continuous image acquisition and rapid, accurate clinical feedback, while operating under strict constraints on computational resources and power consumption. Although deep neural networks achieve high diagnostic accuracy, their substantial computational complexity and memory requirements limit their suitability for on-device inference. In contrast, classical machine learning techniques such as Support Vector Machines (SVMs) offer a more hardware-friendly alternative. This work introduces a resource-efficient hardware architecture for multi-class SVM inference that leverages Posit arithmetic. The proposed design employs a binary classification kernel with a one-versus-rest classification scheme to enable scalable multi-class decision-making while preserving architectural simplicity. By exploiting the tapered precision property of Posit arithmetic, the design enhances numerical stability during dot-product accumulation compared to conventional fixed-point implementations, while also reducing the hardware overhead typically associated with IEEE floating-point representations. Multiple Posit configurations, ranging from (4,2) to (16,2), are evaluated to explore trade-offs among silicon area, power consumption, latency, and classification accuracy on standard biomedical image datasets. Hardware evaluation shows a silicon area reduction of 66.5%, power savings of 64.5%, and a 1.29 × improvement in latency relative to conventional implementations, while still maintaining competitive accuracy. These results indicate that the proposed architecture is well-suited for deployment in next-generation portable and edge-assisted biomedical diagnostic systems.

The rapid proliferation of Artificial Intelligence (AI) has significantly increased the demand for high-performance and energy-efficient Deep Neural Network (DNN) accelerators. Central to these accelerator architectures is the Multiply-Accumulate (MAC) unit, whose efficiency directly impacts overall system performance. Traditional MAC implementations based on fixed-point and floating-point arithmetic suffer from limitations such as large area, high power consumption, and restricted dynamic range, making them suboptimal for modern DNN workloads. Recently, the Posit number system, introduced by Gustafson, has emerged as a promising alternative due to its dynamic precision and reduced hardware complexity. However, empirical studies suggest that while high-bit-width Posit configurations maintain DNN accuracy and offer some efficiency benefits, low bit-width Posit formats result in significant accuracy degradation, limiting their practical utility. In this work, we propose a novel Split-Posit MAC architecture that bridges the gap between low-bit-width efficiency and high bit-width accuracy. By decomposing higher bit-width Posit computations into lower bit-width operations, the proposed architecture incurs a negligible drop in inference accuracy across standard TinyML benchmarks. Furthermore, ASIC implementation validates the practicality of our approach, reporting a 39.89% reduction in silicon footprint, a 39.47% improvement in energy efficiency, and a minor increase in delay. These results establish Split-Posit MAC as a highly efficient and scalable solution for next-generation AI accelerators.

Modern Machine Learning (ML) applications increasingly demand high-precision arithmetic within critical resource constraints. Although standard floating-point arithmetic remains widely used, it incurs huge hardware complexity. The recently introduced Posit format has emerged as a promising alternative, offering improved numerical efficiency with reduced hardware costs. Empirical studies indicate that, although Posit arithmetic units exhibit lower hardware complexity than their floating-point counterparts, they often require higher precision to achieve comparable numerical accuracy, thereby reducing the anticipated savings in resource utilization. To address this challenge, we introduce the Split-Posit format, designed to mimic the benefits of high-precision Posits at significantly lower bit widths, thereby achieving a favorable trade-off between accuracy and hardware efficiency. Furthermore, we propose a specialized digital signal processing (DSP) architecture for embedded FPGAs tailored for Split-Posit arithmetic. Unlike conventional FPGAs that rely on fixed DSP primitives and are ill-suited to Posit’s variable-length field structure, the proposed architecture enables more efficient resource utilization. Experimental results show that the proposed design achieves 53.1\(\%\) savings in fabric area, 61.1\(\%\) lower power consumption, and a 48\(\%\) reduction in critical-path delay per multiply–accumulate (MAC) operation compared to state-of-the-art (SOTA) implementations. The architecture is validated using standard benchmarks, demonstrating competitive performance and superior hardware efficiency, making it well-suited for next-generation reconfigurable systems-on-chip (SoCs).

Piece-wise polynomial approximation - linear (PWL) and quadratic (PWQ) have proven to efficiently implement non-linear functions on hardware. This paper introduces Hybrid Piece-wise Polynomial Approximation (PW-Hybrid) where pieces of approximation for a function are obtained as the best combination of linear and quadratic polynomials, such that the error converges to the desired minimum. The hardware for PWL, PWQ and PW-Hybrid designs are further refined using Particle Swarm Optimization (PSO) algorithm to fine-tune the quantized bit-widths for realizing coefficients of the polynomial employed. This PSO optimised hardware design is evolved for a range of non-linear functions including i) Piece-wise polynomial linear optimized (PWLO) - Logarithmic, Hyperbolic-Tangent, Sigmoid and Softsign, and ii) Piece-wise polynomial quadratic optimized (PWQO) Exponential, and iii) Hybrid Piece-wise Polynomial optimized (HyPPO) - Sine and Sinc. The proposed design shows considerable decrease in hardware resource consumption and critical path delay, when synthesized using Cadence 45nm gpdk library. Highest improvements in HyPPO, PWLO and PWQO designs, are observed for Sine, Logarithmic and Exponential functions, with 65.06%, 24.47% and 9.67% gain in power-area-delay product (PADP) respectively, when compared with SOTA - PWL and PWQ designs. The proposed methods also exhibited minimal inference accuracy loss when tested on popular CNN architectures.

Recent advancements in arithmetic systems have emphasized the need for faster, resource-efficient operations without compromising on the range or accuracy provided by the IEEE 754 floating-point format. Consequently, the Posit number system has gained attention for its computational efficiency and broader dynamic range. However, multiplication remains one of the most computationally expensive operations in Posit arithmetic, with traditional multipliers suffering from additional overhead due to complex decoders. This paper proposes a novel and efficient Posit multiplier architecture that addresses these challenges by modifying the conventional decoder. Specifically, we introduce multiflag priority encoders to streamline the decoding process, thereby leveraging the silicon footprint utilized by the design and benefiting critical path delay. We also present a modified multistage Booth encoding technique, optimized for the Posit format, to enhance multiplier speed without compromising on accuracy. Additionally, the clock-gating technique applied to the multi-level encoding architecture selectively disables clock signals during idle cycles, ensuring further savings in power. The combination of new decoders and power optimization strategies establishes a hardware-efficient Posit multiplier, which was validated for a DCT compression application. Implementation results demonstrate that the proposed Posit multiplier offers power savings up to $46 \%$ with respect to the state-of-the-art (SOTA) Posit and other floating-point multipliers. Furthermore, the proposed architecture achieves a $48 \%$ silicon footprint savings. The hardware efficiency of the proposed Posit multiplier, along with the acceptable DCT-compressed image quality results, validates the novel contribution and its effectiveness. All the design files are made freely available for further usage by the designers and research community.

Convolution is a fundamental filter operation employed in neural networks to extract the most discriminative features. Convolution is a compute and data-intensive operation that usually demands redundant access to data and kernel weights. To address these challenges, we present a novel Vectored Processing Element configured Systolic Array (VPSA) architecture generator, with a new kernel loading scheme that completely utilizes all generated partial results. The proposed design adopts a weightstationary dataflow architecture to minimize kernel memory access overhead and utilizes vectorized processing elements to increase the throughput significantly. For a kernel of size K, the VPSA architecture achieves a throughput close to K for large input images. The architecture is implemented and evaluated on the Zynq Ultrascale+ MPSoC ZCU102 platform and benchmarked against existing state-of-the-art designs. The proposed design is able to achieve a peak-throughput of $1415.29 \mathrm{GOP} / \mathrm{s}$, higher than the SOTA results. Additionally, a hardware-software co-optimization strategy is employed to analyze performance trade-offs based on the placement of input/output interfaces and the Systolic Array (SA) within the Processing System (PS) or Programmable Logic (PL) sections of the ZCU102 FPGA platform. The SA generator framework is made freely available for easy adoption and further usage by the researchers and designers community.

Approximate computing offers a powerful solution to reduce power, area, and computational effort in arithmetic units, making it highly suitable for energy-efficient edge applications. However, designing approximate multipliers that sustain acceptable accuracy across diverse workloads such as image compression, machine learning, and audio processing remains a major challenge. To address this, we propose a novel design space exploration methodology that applies encoder-level approximation in Booth multipliers partial product stage for both 8bit and 16-bit configurations. For 8-bit designs, we define four encoder schemes: one exact and three approximate, and generate 256 combinations. Each is synthesized using OpenROAD with Nangate45 nm technology node and evaluated based on silicon footprint, power, and delay metrics. Application-level quality is assessed using SSIM for JPEG compression, inference accuracy for machine-learning design, and corresponding hardware metrics for the multiplier design combinations. For a 16-bit multiplier design, a multi-objective optimization technique was employed to evolve the most balanced architecture across hardware metrics and application-specific$\mu$-Law encoding & decoding output parameters, including SNR, and standard deviation error. The best configurations are compared against multipliers from state-of-the-art (SOTA) designs. Results demonstrate that our approach yields compact, high-quality multipliers that surpass existing designs across multiple domains, offering a viable path for deployment among edge AI systems. All designs are made freely available for further usage and easy adoption by researchers and designers [1].

Approximate computing involves trading precision for improved performance in applications where exact accuracy is not essential. This study explores approximate computing in floating-point multipliers for Weight Stationary Systolic Arrays, examining IEEE 754 (FP32), TensorFloat-32 (TF32), and Brain Floating point (BF16) formats. We combine column truncation with positive and negative compressors to optimize computation efficiency versus accuracy. Using NSGA-II algorithm to explore design configurations, we achieve significant hardware improvements while maintaining high output quality. Testing across image processing kernels and CNN layers shows improvements of up to 28% in critical path delay, 69% in silicon footprint reduction, and 66% in power savings, while preserving high structural similarity (SSIM) values. The approach demonstrates that strategic approximation in floating-point multiplier design can substantially enhance hardware accelerator efficiency in error-tolerant applications. By balancing precision sacrifices against performance gains, we establish a viable method for optimizing hardware resources in modern computing architectures.

Low latency inference is a highly desirable metric to deploy any autonomous control systems. To aid in this field, we propose and investigate multiple spike decoders for Spiking Neural Networks (SNN) to perform forearm angle prediction by taking Surface Electromyography (sEMG) signal as input, as part of an autonomous post stroke motor rehabilitation system. The proposed regression decoders are compared with the existing implementations and conventional ANNs in terms of accuracy and relative efficiency. The models introduced here exhibited an accuracy of 90% compared to the baseline’s 82% while also offering 10× to 12× of higher energy efficiency and EDP gains 24×. These models also exhibited relatively lower loss in performance with varied input data parameters compared to the baselines. These SNNs are a low latency alternatives for implementing complex regression models like the reference rehabilitation system with potential usability in other Reinforcement Learning (RL) problems.

Finite field polynomial multiplication for large operand sizes forms the building block for designing modern Cryptography Systems. This work presents two new approaches to realize three-operand multiplier architecture for Galois Field (2N) polynomial operations, referred to as Cascade and One-Shot Mixed mode configurations. A meta-heuristic approach enabled with a single-objective fitness run was employed to design optimal solutions in the form of non-homogeneous recursive sequences in Karatsuba multiplication, targeted for three-operand multiplication in Galois Field (GF). During the optimization runs, the candidate design solutions were hardware characterized through ASIC process using Cadence Genus tool with 45 nm technology library files. The proposed architectural designs offered improvement in compute-latency of 12.77% and footprint complexity of 61.97% with benefits in the area-delay product (ADP) of 70.72%, and power savings of 83.62% and 51.23% improvement in PPA compared to the existing state-of-the-art (SOTA) designs. All the hardware design files are made freely available for further usage to the designers and researchers community.

Efficient polynomial multiplication in finite fields is vital for the design of high-performance on-chip cryptosystems. This need becomes even more significant in modern digital security systems that demand enhanced security strength and computational efficiency. Elliptic Curve Cryptography (ECC) is a public-key cryptography method that effectively balances security and performance using shorter key lengths. Recent developments in polynomial multipliers utilize various strategies, such as recursively splitting operand bits and using a blend of Karatsuba and overlap-free multipliers to recombine partial products. This mixed approach has demonstrated hardware and performance advantages over state-of-the-art techniques. Heuristically optimizing polynomial multipliers for ECC involves a design-space search using meta-heuristics to find optimal recursive configurations based on hardware parameters. The ECC processor is specifically engineered to incorporate these optimized polynomial multipliers. The design is implemented on a ZYNQ ZU-19EG FPGA board and synthesized using the Cadence Genus tool with a 45 nm technology node. This approach results in a 52.45% reduction in footprint, a 52.50% decrease in critical path delay, and a 73.19% improvement in the area-delay product. These improvements lead to a more hardware-efficient design, contributing to tighter and more secure cryptographic systems. The designs are freely shared with the research community for further use.

Long short-term memory (LSTM) has emerged as a definitive network model for analyzing and inferring time series data since their introduction. LSTM has the capability to not only extract spectral features similar to convolutional-neural-network (CNN) models but also a mixture of temporal features. Due to this distinguished advantage, similar feature extraction method is explored for the spiking counterpart of the neural network, targeted for time-series data. Though LSTMs perform well in the spiking form of neural network, they tend to be compute and power intensive. Addressing this issue, the work proposes multicompartment leaky (MCLeaky) neuron as a viable alternative for efficient processing of time series data. The MCLeaky neuron, introduced as a derivative of the leaky integrate and fire (LIF) neuron model, contains multiple memristive synapses interlinked to form the memory component of the neuron, by emulating Hippocampus’ structure of brain as reference. The proposed MCLeaky neuron-based spiking neural network (SNN) model and its quantized variant were benchmarked against state-of-the-art (SOTA) spiking LSTMs to perform human stress detection by comparing computing requirements, compute-latency, and real-world performances on freshly acquired unseen data with models that is acquired by employing neural architecture search (NAS). Results show that the networks with MCLeaky activation neuron managed a superior accuracy of 98.8% to detect stress based on electrodermal activity (EDA) signals, better than any other investigated model, while using 20% less parameters on average. MCLeaky neuron was also investigated for different modality of signals, including EDA Wrist, EDA Chest, Temperature, electrocardiogram signal, and combination of them. Quantized MCLeaky model was also derived and validated to forecast their performance on hardware aware architecture, which resulted in 91.84% accuracy. The neurons were evaluated for multiple modalities of data toward stress detection, which resulted in energy savings of$25.12\times - 39.20\times $and EDP gains of$52.37\times - 81.9\times $over the artificial neural network model, besides offering the best accuracy of 98.8% when compared with the remainder of the SOTA implementations.

Complex Independent Component Analysis (c-ICA) is widely employed in many applications involving MIMO communication systems, radar signal processing, medical imaging (MRI), and other fields where data is represented in complex number format. This paper proposes a configurable fixed-point pre-processing hardware accelerator for c-ICA algorithm that offers a balanced combination of high throughput with low area and power costs. The proposed accelerator performs the c-ICA pre-processing in multiple stages including a step for centering and covariance matrix computation, followed by eigenvalue decomposition (EVD) and whitening matrix computation units. The datapath flow is pipelined in such a way that each stage in the path is operated in parallel and individual stage designs are pipelined within, resulting in high throughput. The paper characterizes the proposed architecture design using 45 nm process flow and compares its performance with the current state-of-the-art (SOTA) designs. Experimental results showcase substantial savings in processing time and computational resources, making it highly suitable for real-time and resource-constrained applications. A throughput gain of 49.96% and complexity reduction of 22.23% and 19.63% for covariance cum centering and EVD units respectively was achieved by the proposed design over the best of the SOTA designs. The hardware design files are made freely available for further usage to the designers and researchers’ community [1].

Neurosurgery is a highly complex, intricate procedure performed by a trained neurosurgeon with a blended aid of radiological imaging and cutting-edge technologies. Neurosurgery is considered a highly challenging and demanding task, and automated recognition of surgical steps from live video feed is expected to aid neurosurgeons in making informed procedural decisions. Besides, the autonomous phase recognition is essential in developing intelligent operating theatres to better the outcome of the surgery, and thereby improve patient’s life post surgery. Phase recognition and characterization facilitates in accounting the overall summary of the surgical procedures and helps in not only assessing the skills of the surgeon but also helps to relate the surgical procedures with the outcome for future reference. Computer vision based phase recognition of the neurosurgery is a step towards making autonomous characterization of the complete surgery and later integrate the same model for the development of context-aware neurosurgical robotic assistant. Deep learning techniques in the form of Dense convolutional neural network followed by an LSTM (Long Short Term Memory) presented phase recognition accuracy of 83.6% which is the best among the state-of-the-art (SOTA) feature extractor methods available. Acceptable inference rate was characterized for the live microscopic-surgical videos, which satisfies the needs of neurosurgical practices.

Achieving energy-efficient arithmetic operations is crucial for sustainable circuit design in modern digital systems. One computational bottleneck is the multiplication of operands with unequal bitwidths, which often necessitates zero-padding and leads to unnecessary hardware overhead and power dissipation. This work tackles this challenge by proposing an optimized asymmetric bitwidth multiplication framework. The framework determines the optimal split for asymmetric multiplication by considering the product of critical path delay, silicon occupied area, and power incurred by the design (PDAP) as the fitness function. Compared to conventional 64x 64 bit padded multi-plication for unequal operand bitwidth, the optimized 64 x 32 bit asymmetric multiplication achieves an impressive 79.73% gain in PDAP. Furthermore, the heterogeneous split approach outperforms the homogeneous 64 x 32 bit multiplication of equal 32–32 bit splits by 13.83% in PDAP, highlighting the advan-tages of heterogeneous splitting for asymmetric bit widths. The proposed framework is validated up to 128 bits, starting from 16-bit, by incorporating splits of both even and odd bit widths. Engineered with a particle swarm optimization (PSO) technique, the framework handles multiplication between operands of any bitwidth, making it a unique and versatile solution for applications requiring efficient asymmetric bitwidth multiplication, such as sustainable circuit design. The multiplier design framework and files are freely available for researchers and designers in the community.

The proposed piece-wise-linear (PWL) method utilizes the Method of Least Squares to implement transcendental functions such as Sigmoid and Hyperbolic-Tangent with control-lable Maximum Absolute Error (MAE) in hardware. In addition, the quantization process is emulated in software to determine the fractional bit size required for hardware realization without introducing additional truncation errors. This enables effective control of error characteristics by designers. Implementation is carried out in sign-magnitude fixed-point and IEEE 754 half-precision floating-point formats in hardware. An Application Specific Integrated Circuit (ASIC) synthesis is performed using Cadence's gpdk 90 nm technology nodes for hardware characterization of realized functions using the novel method. The proposed PWL implemented Sigmoid function resulted in 6.77% improvement in MAE, with 41% less delay and 70.6% power savings over the best of the SOTA works reported so far. Similarly, the proposed approximated Hyperbolic-Tangent function illustrated 10.3% better MAE, with 10.3% less delay and 45.3% power savings. The proposed PWL factored activation function was further evaluated in AlexNet model to exhibit similar training and validation accuracy as that of the exact function. Overall, the proposed PWL realized approximate function is established as a power-efficient and precision-effective design. These designs are a step towards building power efficient hardware accelerators for AI workload. All the hardware designs are made freely available for further usage to researchers and designers community.

Network architecture search (NAS) is a tedious process and hence a different approach to train a large over parameterized network, followed by a progressively shrinking algorithm towards targeting the best efficient models for hardware platforms is practiced, which is referred to as Once-For-All (OFA) network. This paper focuses on utilizing OFA-defined NAS runs on ResNet topologies for wide range of hardware platforms ranging from workstations CPU, GPU, mobile CPU, GPUs, VPU, and DPU run on Xilnx FPGA. The OFA extracted model runs on the VPU unit offers speed improvement of 86% and 46% over mobile CPU A76, and mobile GPU 630 system respectively. The latency improvement of 100% was achieved for 3-threaded execution over single-thread for the DPU unit. Roofline model of OFA defined NAS extracted ResNet topologies indicated that all models are compute-bound when operated on Threadripper 960X CPU workstation; with 16-threaded execution offers maximum performance for batch size of 16. For GPU workstation, a throughput improvement of 66.66% to 100% was achieved for the OFA NAS generated models when configured to run on 3-threads over single-thread. Roofline performance analysis for the OFA NAS extracted model running on a Xilnx FPGA ZCU102 showed that most of the models are compute-bound for single and multi-threaded execution.

In the rapidly advancing landscape of computing, hardware accelerator designs are pivotal for satisfying high performance and low power demands. Systolic array (SA) architectures, tailored for general matrix multiplication (GEMM) operations, are ideal for image processing workloads. In this work, an integrated MAC (IMAC)-factored SA is proposed. Unlike prior focus on standalone multipliers and adders, IMAC optimizes multiplier-and-accumulator (MAC) units. The new IMAC approach was introduced to three category of Processing Elements (PE) that define SAs, and were further evaluated against four state-of-the-art (SOTA) SA designs. IMAC-SA reported noteworthy advantages: a design footprint reduction of 17.30% to 26.40%, power savings from 5.46% to 15.85%, and a maximum critical path delay improvement of 9.47% over other SOTA designs.

Reliable and low-power stress-detector ‘at the edge’ is extremely beneficial for continuously monitoring hospitalized patients. In this context, feed-forward spiking neural networks (SNNs) for stress-detection using physiological time-series signals of electrodermal activity (EDA), body temperature, and a multi-modal signal comprised of both, are designed and evaluated.

Modern FPGAs, equipped with heterogeneous blocks (H-blocks) offer design flexibility, enabling the implementation of complex designs with minimal effort. Custom-embedded fabric in System-on-a-Chip (SoC) has recently been envisioned to secure an IP block through the entire flow from design to manufacture, which involves multiple vendors. Hence, new design strategies for deducing efficient embedded-FPGA (eFPGA) architecture blocks targeted toward specific workloads need to be investigated. This work applied Genetic Algorithm (GA) to generate the most optimal H-block-defined FPGA layout to achieve the best hardware objectives, including critical path delay, resources utilized, and power consumed for the benchmark under test. The strategic placement of memory, digital signal processor (DSP) slices, and configurable logic blocks (CLBs) targeted for attaining minimum area-delay-product (ADP) for the benchmark-under-test, on the given layout forms the crux of this work. This novel framework was applied to different machine learning (ML) and non-ML benchmarks to characterize its performance against other state-of-the-art (SOTA) FPGA architectural layout designs. The proposed work showcases a maximum of 35% ADP gain for one of the benchmark design runs over the SOTA-designed layout. The ideal fabric layout architecture is a step towards securing IP on an eFPGA block, which is not disclosed to other vendors and configured as per the targeted workload post-fabrication of the chip.

Accurate depth estimation is a fundamental challenge in robotics and computer vision, crucial for applications ranging from autonomous navigation to complex object manipulation. While traditional techniques such as RGBD cameras and 3D Lidar systems provide high precision, their high costs and computational demands restrict their use in many scenarios. Conversely, monocular depth estimation (MDE) offers a more affordable solution but often struggles with depth accuracy and real-time performance. In response, this research introduces a novel convergence-based stereo vision system that leverages two independently movable cameras for dynamic depth estimation. The system facilitates depth tracking of any selected object by adapting camera orientation and extrinsic matrices to achieve millimeter-level accuracy with less than 1 % error in depth estimation over 5 meters, which is significantly better than few state-of-the-art Stereo systems that offer up to 2% error over a similar range. ArUco tag-based calibration mechanism was used to improve accuracy due to precise angle calculation. Further, the system successfully tracks and localizes multiple human body joints simultaneously using the Google Mediapipe Joint Detection model, providing a 3D approximation of the subject's position concerning the system in real-time. This approach not only offers a cost-effective and precise solution for real-time depth perception but also opens new avenues for dynamic, high-resolution environmental interaction in robotics.

Paralysed patients find it hard to move various body parts depending on the severity of the injury. In an attempt to recover the motor imagery skills, rehabilitation schemes are recommended. One of the biggest barrier is the continuously dropping motivation for performing physiotherapy, besides the logistics hardships constantly borne by the care-taker. While the latter challenge remains personal, various Human-Computer-Interaction (HCI) emerged applications have shown promise to maintain the zeal to continue the therapy. Eye Tracking has been one of the popular interfaces to the HCI based rehabilitation gaming engines. Besides eye tracking also serves as a measure to evaluate the degree of neurological disorders and recovery from the same. Vision based eye-tracking exists but are cost ineffective, besides being a privacy-disabled solution. Alternately, (Electrooculogram) EOG signals to track eye movements for HCI purpose has emerged and have shown potential. This work establishes real-time EOG signal devised eye and blink tracker system. Two channels of EOG signals are collected and supplied to motion tracker model. Random forest and LGBM classifier models with an accuracy of 96% were found suitable for real-time tracking. For pilot demonstration, the proposed EOG signal tracker system was interfaced with a rotating camera system that follows the eye movement to provide 360 °of vision at 2 ° resolution. The real-time use-case of EOG eye tracker system paves way for integration with much more finer physiotherapy applications for paraplegia patients. The design files and EOG datasets for eye-tracking are made freely available for further usage to the researchers and users.

POSIT offers a wider dynamic range when compared to floating-point (FP) formats with lesser number of bits. Such data formats are required to address the need for low-bit high-precision hardware architectures for neural networks (NNs) on edge platforms. Activation functions (Af) which introduce non-linearity during the feature extraction process remain as a core component for realizing NN systems. CORDIC (COordinate Rotation Digital Computer) architecture is a hardware efficient technique to realize complex non-linear functions and is deemed suitable to implement Afs. Hence, this work aims to investigate POSIT data formatted CORDIC architecture to realize Afs (Tanh, Sigmoid and Softmax) in different architectural styles. A benchmark evaluation for the proposed POSIT data formatted Afs with the improved CORDIC architecture over SOTA (IEEE 754 FP formats) based designs are presented. The noticeable improvement in hardware design space and error metrics makes the CORDIC architecture-based POSIT formatted Afs stand out over other methods. All the design files are made publicly available for easy adoption and further usage to the designers’ and researchers’ community.

Reliable, low-power stress-detection ‘at the edge’ is important in the context of monitoring post-stroke patients. In this context, we have developed feed-forward spiking neural networks (SNNs) for stress-detection using physiological timeseries signals of electrodermal activity (EDA), body temperature, and a multi-modal signal comprised of both. Execution of the SNNs on Intel Loihi-2 (a neuromorphic research chip) showed 5× to 83×, and 9× to 123× better energy-delay product (EDP) compared to equivalent ANNs executed on a low-power edgeGPU, and FPGA respectively. We report that the largest EDP gains (83×) are obtained for the multi-modal SNN, which has „9× less number of parameters and is „9× faster in inference latency than a conventional ANN executed on an edge-GPU.

Hardware-efficient polynomial multipliers are desired to satisfy the ever-growing demands of computing within the finite field space toward developing a strong cryptosystems. This research meticulously explores polynomial multiplication from the context of algebraic structures by introducing a novel hetero-blend recursive multiplier that harnesses the strengths of the contemporary state-of-the-art (SOTA) designs. The heterogeneous-blend recursive multiplier (HRM) adeptly merges the footprint efficiency of the Karatsuba multiplier (KM) and the compute-latency benefits of the overlap-free KM (OKM) at higher stages, while at lower bounds, it capitalizes the optimal balance of footprint and compute-latency benefits of the schoolbook multiplier (SBM). To further enhance the performance, HRM integrates the heterogeneous term division throughout its stages which is a characteristic find taken from the prior work on$M$-term nonhomogeneous Karatsuba multiplier (MNHKA). Furthermore, a MATLAB framework has been devised to expedite the exploration process in the finite field design space resulting from the heterogeneous usage of the$M$terms across multiple stages. The presented HRM design undergoes comprehensive evaluation when benchmarked against contemporary SOTA designs including KM, OKM, their corresponding homogeneous$M$term variants referred to as$M$-term Karatsuba multiplier (MKM),$M$-term OKM (MOKM) alongside recent variants of composite$M$-term Karatsuba multipliers (CMKA), MNHKA, and equivalent overlap-free variant$M$-term nonhomogeneous overlap-free Karatsuba multiplier (MNHOKA). The field-programmable gate array (FPGA) synthesized results for the HRM designs on Zynq ZCU-104 board showcase a best-case of 17.288% lookup table (LUT) savings, 5.68% reduction in delay, and 20.88% gain in area-delay product (ADP) compared with the optimal SOTA design, while also revealing a 13.49% reduction in LUT usage, 5.45% decrease in delay, and 12.97% improvement in ADP when compared with the best among MNHKA and MNHOKA designs. Furthermore HRM designs synthesized on the Cadence GPDK45 library achieved a best-case footprint saving of 16.18%, a critical path delay improvement of 29.53%, a remarkable 45.66% gain in the ADP, a substantial 30.37% reduction in power consumption, and a noteworthy 38.63% improvement in power per area when compared with the optimal SOTA design. In comparison to the leading MNHKA and MNHOKA designs, the HRM designs exhibit a best-case footprint improvement of 5.77%, 8.31% reduction in delay, 16.76% enhancement in ADP, a significant 20.18% power savings, and a notable 17.71% improvement in power-per-unit-area (PPA). To catalyze ongoing research and innovation, hardware designs assessed in this article are made publicly available for further usage.

Standard cell design is a challenge considering its impact on the overall synthesis of the design. The standard cells are generally offered by the manufacturers and the cells are updated to match the advancement in the fabrication facility. However matching of the system designed by the non-manufacturing team with the standard cells may not always present the best results. The exploration of standard cell design is very limited and not much is disclosed due to intellectual protection (IPs). This paper proposes a graph-search algorithm to extract the popular set of connected nodes, where the graph represents the computational subsystem and the nodes reflect individual gates. The proposed graph-search approach was applied on MAC designs of different bit-widths to extract top four ranked custom cells of four inputs and further characterized to incorporate them in the CMOS implemented standard cell library. The extracted top four cells were optimized for transistor widths to three different targets including critical path delay, product-of-power-and-delay (PDP), and equal rising and falling resistances separately. The augmented library with extracted custom cells was applied for synthesizing MAC design of four different bit-widths using three different set of library cells. The custom cells in the range of 38.23% to 52.80% were mapped in the synthesized versions of MAC designs for all the three optimized versions of cells, which validates the approach and emphasizes the need to explore new cells for acquiring performance and power-efficient subsystem designs. The standard cell library incorporated with custom cells offered maximum performance improvement of 35.3% and power savings of 56% over the standard cell library when synthesized for MAC designs of different bit-widths. The custom library synthesized MAC designs when adopted as hardware accelerator units for LeNet, AlexNet, and VGG-16 network showcased a performance gain of 23% to 33.80%, over the MAC designs synthesized by the original standard cell library. The graph-search approach is a step towards automating the custom cells for the design under synthesis. The approach has the potential to realize complex functions with customized cells, applicable to modern day SoC design.

Convolution Neural Network (CNN) accelerator designs have a plethora of applications but they account for high computational complexity and demand huge resources. The challenge is to attain reduction in various hardware parameters in size-constrained edge inferencing systems. Multiple methods such as using approximate multipliers, or systolic arrays or quantization techniques, to name a few, were experimented on, previously, to achieve the same. But, one of the important layers in a CNN is a pooling layer where the feature map size is reduced based on a predefined scheme. These pooling schemes play a prominent role in determining the accuracy obtained and also affect the hardware usage in accelerator designs. This paper discusses the hardware design of two new pooling methods, Binary Weighted Absolute Deviation (BWAD) and Absolute Maximum Deviation (AMD) which showcase promising results in terms of area, delay, area-delay-product (ADP), and power-delay-product (PDP), and also maintain comparable accuracy with that of the existing state-of-the-art (SOTA) methods, Max and Absolute Average Deviation (AAD) pooling. The proposed pooling schemes make use of the best features in the existing methods such as calculating absolute deviation between consecutive pixels for maintaining fairly comparable accuracy and consist of simple designs, without the use of multipliers or dividers, when mapped on to hardware. The two pooling methods are validated by incorporating the corresponding layers in multiple CNN architectures and datasets for fair evaluation. The hardware efficiency of the pooling methods is investigated by synthesizing on Zynq 7000 series Zedboard (FPGA). ASIC flow synthesis results are obtained from Cadence Genus tool for 45 nm and 130 nm technology nodes. Hence, both the proposed pooling schemes are potential candidates for designing on-chip neural network hardware accelerators which exhibit a fine balance between network accuracy and hardware benefits.

Multiply-and-accumulate (MAC) units are primarily utilized for convolution operations targeted towards signal and image processing workload. The compressors are applied at the partial product reduction stages to extract the multiplier output bits, which are later accumulated with an extra adder unit. The paper proposes an integrated approach where the other operand of the MAC unit is directly fed to the partial-product-matrix (PPM) before the product bits are evaluated. This integrated Multiplier-and-Accumulate (IMAC) approach saves an additional adder unit and instead extends the compressor, which is already used to reduce partial-product bits of the multiplier design. Compressors employed exact and approximate IMAC architectures were designed and evaluated through ASIC and FPGA flow. Five versions of inexact IMAC design were independently compared with traditional one-level approximation and two-level approximation in MAC designs. The proposed work is found to be hardware efficient when compared with state-of-art MAC units. The error metrics were either comparable or better for IMAC design when compared with separately designed approximate multipliers followed by exact or approximate adder units. The image blending application was considered to measure the quality metrics. The proposed IMAC design files are made freely available for further usage by the research and development community.

Systolic array (SA) is an architecture which is conceptually similar to an arithmetic pipeline and is created by uniformly connecting group of identical data processing elements (PE). Approximate computing benefits in hardware and performance, but incurs accuracy loss, thereby limiting it to error-resilient applications. Majority of inexact multipliers offer one-sided Error Distribution (ErD), and SA architecture with such multipliers results in large accumulated errors. This paper investigates SA architecture with various arrangement of approximate multipliers (AM) with dissimilar ErD for image smoothing and outline extracting applications. Among all the patterns, the Ring arrangement comprising of AMs with opposite-sided ErD placed in nested loops of the SA, was found to accelerate performance by 22.31%, and enhance image quality metrics by 18.15%. For FPGA implementation, alternate arrangement with equal number of AMs with opposite-sided ErD in the SA offered 12.14% LUT savings and comparable flip-flops usage when compared with one-sided AMs in the SA.

The current polynomial multiplication is built on conventional CMOS cells, and no major changes are explored in the standard cell library to improve the performance. Hence state-of-the-art (SOTA) finite field multipliers of operand sizes ranging from 93 to 409 bits were designed and evaluated by adopting faster XNOR cells. The hardware metrics in the form of gates usage, and propagation delay were compared. The SOTA multipliers of different approaches including Conventional Algorithm~(CA), Karatsuba Algorithm~(KA), Overlap free Karatsuba Algorithm~(OKA), and Overlap-free based multiplication strategy(OBS) were designed and synthesized through ASIC flow using 45~nm GPDK library files. The fast XNOR cell adopted SOTA multipliers improved the compute delay in the range of 8.24% to 33.45%, 8% to 37.05%, 4.63% to 18.36%, and 1.01% to 38.73% for OKA, OBS, CA, and KA respectively. All the design files are made freely available for further usage to research and designers' community.

Conventionally, evaluation for the diagnosis of Autism spectrum disorder is done by a trained specialist through questionnaire-based formal assessments and by observation of behavioral cues under various settings to capture the early warning signs of autism. These evaluation techniques are highly subjective and their accuracy relies on the experience of the specialist. In this regard, machine learning-based methods for automated capturing of early signs of autism from the recorded videos of the children is a promising alternative. In this paper, the authors propose a novel pipelined deep learning architecture to detect certain self-stimulatory behaviors that help in the diagnosis of autism spectrum disorder (ASD). The authors also supplement their tool with an augmented version of the Self Stimulatory Behavior Dataset (SSBD) and also propose a new label in SSBD Action detection: no-class. The deep learning model with the new dataset is made freely available for easy adoption to the researchers and developers community. An overall accuracy of around 81% was achieved from the proposed pipeline model that is targeted for real-time and hands-free automated diagnosis. All of the source code, data, licenses of use, and other relevant material is made freely available in [1]. Clinical relevance- Detection of Self-Stimulatory behaviors from recorded videos forms a key step towards the development of automated and cost-effective technology for screening early diagnosis and tracking of developmental disorders from The authors thank the psychiatrists at Bubbles Center for Autism, India for providing us with annotations for the videos in the SSBD+ dataset. The authors acknowledge the support and the research grant from IBM GUP.

Approximate computing in the hardware design space has gained attention owing to the significant benefits achieved in power savings, performance improvement, and compact spacing. Most of the arithmetic operations including addition, multiplication, division, and even a few of the activation functions are realized using approximate computing techniques in the past. These are primarily applicable for error-resilient image processing applications where the visual perception of humans has limited abilities to distinguish between the original and approximated image. This has been extended to other signal-processing domains under similar constraints on human sensing modalities. Although most of the work intends to apply approximate computing on Artificial Intelligence (AI) workloads, but realizing approximate computing on the same has not been feasible. Hence, this has deprived to feel the impact of hardware benefits in conjunction with network accuracy compromises. This research work aims to establish the adoption of a specific set of approximate multipliers in the Convolutional Neural Network (CNN) and present hardware characteristics along with the validation accuracy of the network. Eight different approximate multipliers that are categorized along the positive and negative error distributions are applied to 6-layer, 3-layer, and 1-layer CNNs that are trained on benchmark datasets of CIFAR-10, MNIST, and F-MNIST respectively. The extensive design space exploration has allowed extracting the optimal sequence of approximate multipliers along different layers of CNNs reporting hardware gain and least accuracy drop. For the 6-layered CNN, the optimal hardware design with approximation applied for 1st, and 3rdlayer offered hardware gains of 16.5%, 10.2%, 2.4%, and 18.2% in power, footprint, delay, and PDP respectively, with comparable validation accuracy as that of exact CNN. Similarly, the best 3 layered approximated CNN model offered an improvement of 38.09%, 31.57%, 5.97%, and 43.84% in power, area, delay, and PDP parameters respectively over exact CNN model, without much drop in the validation accuracy. The 3 layered CNN demonstrated alternate arrangement of positive and negative error distributed type of multipliers along the layers to minimize the errors and maintain model accuracy close to the original exact multiplier adopted model. The correlation between five different error metrics for the sequence of approximate multipliers applied along the layers of CNNs and the overall accuracy loss in network inference were computed. The proposed work sets an example to leverage any approximate multipliers along the layers of CNN in the future and estimate the most optimal hardware design alongside retain the original network accuracy. The work is a step towards designing custom power-performance-area efficient neural network accelerators.

In the constantly evolving field of multiplication architectures, the Karatsuba algorithm and its extensions have captivated the minds of researchers with their performance metrics. One such optimized design is the Overlap-free Karatsuba (OKA) algorithm which has emerged as an innovative architecture, specifically aimed at enhancing power, performance, and area (PPA) parameters. In this paper, we introduce a novel technique referred to as M-term Non-Homogeneous Hybrid Overlap-free Karatsuba polynomial multiplier (MNHOKA), which surpasses existing state-of-the-art (SOTA) designs, including Karatsuba multiplier (KA), M-Term Karatsuba-like multiplier (MKA), Composite M-term Karatsuba-like multiplier (CMKA), and Overlap-free Karatsuba multiplier (OKA), across various operand sizes. In this paper, a detailed analysis of the proposed MNHOKA and its corresponding M-Term Non-homogeneous Hybrid Karatsuba Algorithm (MNHKA) is presented, highlighting its performance improvements on both Cadence 45 nm process and the ZYNQ ZCU-104 FPGA board for popular bit widths. In ASIC implementations, MNHOKA achieves significant ADP improvements of 28.33%, 28.99%, 58.23%, and 11.95% for operand sizes of 128, 232, 282, and 750 bits, respectively, compared to the best-case SOTA design. Furthermore, our method yields lower power consumption. When comparing FPGA results of the proposed MNHKA design with the best-case SOTA works, ADP improvement of 22.72%, 16.10%, 2.52%, and 11.36% improvement was achieved for the respective bit-widths of 128, 232, 282, and 750 bits respectively. The advantages of the proposed MNHOKA, along with its equivalent MNHKA design variants, are evident in their superior hardware characteristics over existing SOTA designs. This research represents a significant step towards realizing efficient Cryptosystems in the immediate future. To foster further research and innovation, we have made the hardware design files freely available to the researchers and designer community.

Approximate computing is an emerging method-ology that offers hardware benefits when compared with the traditional computing design at the cost of accuracy. It is highly suitable for applications which does not require precision but rather try to preserve exactness of the outcome. Many arithmetic designs have evolved over the years using approximate methodologies. Square-root is one of the common yet complex hardware unit which is often employed in image processing and communication system design application. However not much hardware implementation of square-root function is seen. In this paper a novel square-root design is proposed that offers better accuracy, and improved hardware results compared to that of the previous works. The proposed design utilizes first two terms of exponent series expansion and applies two level of approximation to evolve not only hardware efficient square-root designs but also offer improved error characteristics. The approximate Square-root design was implemented in all the three data-formats including integer, fixed, and IEEE half precision floating point. The proposed designs were validated on Sobel Edge Detection algorithm and envelope detector for communication design to provide accelerated performance.

Conventional synthesis algorithms transform the behavioral RTL design to a standard cell mapped gate level netlist, with support to customize optimization effort of few operators. HDL description standards and current synthesis methods lack support to generate netlist of custom functions for quick validation and characterization of the design. Additionally, synthesis does not cater directly to various mathematical functions, design efforts towards approximating the desired function is needed. Hence a synthesis method for realizing circuits applicable to not only arithmetic but also to non-linear functions will be highly valuable and appreciated among the VLSI design community. This work employs Cartesian Genetic Programming (CGP) algorithm, an evolutionary design methodology suitable to synthesize digital circuits. CGP benefits in accelerating the design process and offers the ease to realize complex functions with little to no design effort. Activation functions are difficult to realize as combinational circuits using traditional design methods, this work validates the synthesis results for 6 non-linear activation functions using both classical and standard cell synthesis oriented CGP. The ability to incorporate such unconventional designs to the traditional synthesis flow will be instrumental for implementing accelerators in hardware space, and eventually for efficient design of heterogeneous SoC systems.

VLSI implementation of arithmetic functions are of high demand considering the rise in hardware realization of image and digital signal processing modules for various autonomous applications. The hardware implementation offers faster results and desirable outcome, but expecting the same design metrics in the form of power, footprint and delay on a tiny decision-making edge devices with limited resources needs design improvisation. Approximate computing promises to support the required hardware metrics in error resilient applications where the inexact output is not deviated much from the expected one, and decision made remains unchanged. Multiplier design blocks are heavily used in the multimedia functional chip, and introducing approximation in these blocks effectively benefits design metrics and chip cost of the developed system-on-chip(SoC). The proposed work attempts to design and use various sizes of approximate AND-OR re-coded compressors in the multiple reduction stages, along with various fast adders in the final addition stage of multiplier design. Further, design metrics and resources utilized for different multiplier designs were characterized in ASIC and FPGA synthesis flows respectively, along with their error statistics. Designed approximate multipliers were employed in Gaussian smoothing application to evaluate the quality-hardware resource trade-off of approximation

Most of the applications of modern day VLSI designs are approaching towards energy efficient and high speed computing solutions. Approximate computing is considered a suitable design methodology that satisfies the current requirements of hardware and performance metrics without compromising on the outcome significantly. Many of the arithmetic operations are realized using approximate computing techniques, and many successful implementations are reported at system level designs. However divider operations in general are rarely realized in hardware and this needs much attention considering the surge in neural networks implementation in hardware. In this paper, a novel approximate divider is proposed which is not only characterized to have better accuracy and hardware efficient when compared to the other accurate dividers. The proposed divider is built on logarithmic divider and approximates the exponent part to achieve the desired hardware characteristics. The proposed 8-bit, and 16-bit divider design were realized in 45-NM CMOS technology for different input and output data format including integer, fixed-point, and floating-point. The proposed divider was characterized for error and hardware metrics and compared with other dividers. The novel divider was validated on K-means color quantization algorithm, showcasing improved quantization results.

Approximate computing along with quantized low-precision computing has gained significant interest in today’s neural network (NN) implementation. This paper proposes a library of VLSI implementations of different activation functions, aimed towards designing hardware-efficient NN accelerators. Cartesian genetic programming (CGP), an evolutionary algorithm was employed to generate gate-level designs of approximate and exact representations of activation functions. We open-source the hardware library of 9444 circuits containing a majority of the activation functions employed in NN architectures, including Sigmoid, Hyperbolic-Tangent, Gaussian, ReLU, GeLU, Softplus, and Binary-Step. The library also presents the error characteristics and hardware metrics of the designs which will aid in the usage of the library in future research. Additionally a hardware comparison of the proposed circuits against existing implementations including piecewise-linear (PWL), memory-based, hls4ml, DNNweaver implementations to realize activation functions on FPGA and ASIC flow is presented. The CGP evolved hardware library shows minimal silicon space requirement, least power consumption when investigated for ASIC flow, and the least LUT utilization’s in FPGA flow. Besides, SOMALib designs are purely combinatorial, allowing various synthesis stage optimizations towards the target Power-Performance-Area budget, which is not possible in standard memory block implementations.

The ability to decode imagined speech provides further insights in the neuroscience of speech production. One of the prime use case is in catering to the communication needs of speech impaired post stroke patients who are in locked-in state. The proposed work attempts to approach the challenging task of decoding imagined speech using EEG data of a single subject collected from Emotiv Epoc +, a low-cost saline-electrode designed wearable consumer headset. The research problem focuses on two primitive forms of imagined speech activity that includes phonemes and words. For phonemes, data corresponding to 16 imagined phonemes were collected, and for words, data corresponding to two imagined words Yes and No, were collected. 11 distinct time domain features and four frequency domain parameters were extracted from the temporal windowed EEG signal forming feature-set#1, while level-4 discrete wavelet transformation (DWT) coefficients forms feature-set#2. All features from set#1, and set#2 forms feature-set#3. These feature vectors were employed to characterise different combinations of pairwise phoneme classification, presence of bilabial, fricative, nasal phonemes, multi-class phoneme, vowel classification, and binary word classification individually. Random Forest (RF) and K-Nearest Neighbour (KNN) classifiers were applied to measure the classification accuracy. Principal Component Analysis (PCA) was also used to reduce the dimensionality of the data. Electrodes and features important for classification were identified by analysing the trained models. Results were compared to the previously reported works and were found to have higher or comparable accuracy despite using consumer grade headset with fewer electrodes. The work offers insights into imagined speech synthesis using a feasible and domestic grade device, which is significant in the development of low cost speech rehabilitation and treatment methods.

Approximate computing in general has garnered much needed attention in the design community owing to high power saving benefits, and at the same time quick generation of results. Approximate computing as a design technique continues to offer design advantages which is recently ceased by the ever decreasing technology scaling. Approximate computing is mostly applied to arithmetic designs, that has resulted in significant research interests. The paper proposes a reliable and efficient approximate multiplier design, that uses optimized lower part constant OR adder (OLOCA) design and hardware optimized approximate adder with normal error distribution (HOAANED) separately as two variants. The two approximate multipliers derived from OLOCA adder and HOAANED adder were found to be highly power and footprint efficient, and in addition offers performance improvement over other approximate multipliers. The error characteristics for the proposed multiplier designs were evaluated and compared with the existing approximate multiplier design. The proposed multiplier design along with the existing ones were synthesized using 45 nm CMOS technology and results were analyzed. The proposed approximate multipliers were further explored for canny edge detection application, and results for different standard images were found to be highly acceptable showing 99.9% of outcome similar to exact multiplier design.

Learning musical instruments like piano or electronic keyboard on average takes a decade. Currently, learning an instrument requires continuous supervision from a tutor, and it often becomes unrealistic to stay connected with the music tutor for a long time. Online music learning platforms remain unscalable as there is no way for these platforms to verify whether user pressed a key note with the intended finger, which is significant for learning finger based musical instruments. To overcome this, an autonomous system to evaluate and guide in the learning process by continuously tracking finger movements via a non-camera based solution is proposed. Finger press triggers the muscle movements which are detected at the surface of the forearm in the form of surface Electromyography (sEMG) signals. The paper proposes tracking of finger press for 10 seconds on an electronic keyboard using MyoBand [1] wearable device that provided 8 channels of sEMG signals. Eleven time and frequency domain features of sEMG signals were extracted from sEMG signals to classify musical note played by the instrument on corresponding finger press. The feature set was standardized using standard scaler approach, and vector dimensions were reduced by Linear Discriminant Analysis (LDA) method. The resulting reduced dimension data was applied on Random Forest (RF) classifier to report best classification accuracy for our application. Experiments involved single finger press to render a note in the musical instrument, and multiple finger press to define chord sequence on an electronic musical keyboard. Further analysis was performed to maximize the classification accuracy over the number of trials and optimize the position of electrodes for successful identification of musical note played. The proposed method achieves a classification accuracy of 74.25% for 5 musical note played on an electronic keyboard instrument with 4 MyoBand electrodes, and an accuracy of 95.83% with one electrode for identifying between four musical events including two major chords sequence and two musical notes.

The physical discomfort state of passengers in moving public transportation system is often ignored. It is generally assumed to be a safe ride for transport seekers. However, in recent years, attacks to the passengers have increased especially in metropolitan towns, hence an immediate technology intervention is required in this field which is critically ignored so far. The real-time passenger anomaly detection inside the moving vehicle is an apt approach leading towards a safe ride. The detection of a passenger discomfort state needs further integration and synchronization with the built-in modern invigilance system that reports to the emergency response team to rescue the fellow passenger. An automated in-seat real-time system to detect the physical discomfort state of the passengers in moving vehicles is designed and developed. The design involves an array of pressure-sensitive conductive (PSC) sensors embedded in the cushion of the seat, and backrest. The sensors are placed optimally on 15 different positions of the backrest and seat cushions. The in-seat sensory module is easily interfaced with the prototype invigilance reporting system via wireless communication technique to demonstrate the functionality of the complete system. The in-seat sensory design was experimentally tested under the stationary and moving vehicle for several subjects with more than 99% accuracy in reporting physically attacked state successfully. Also, the proposed system mitigates false detection completely, with the low cost and scalable in-seat sensory design. The in-seat pressure-sensitive sensory design-based passenger state identification method is feasible, tamper-less, and easy to install in the current public vehicles.