This paper describes a first prototype of a testbed System on chip (SoC) to design and evaluate different Neuromorphic Deep Neural Networks (NN) cores. The$1.25mm\times 1.25mm$SoC was fabricated in a 65nm CMOS technology and implements a system composed of an ARM based microprocessor, two memory banks of 32KB, a QSPI serial interface and two NN accelerators. The first one is a novel neuromorphic accelerator consisting of a$5\times 5$kernel Symmetrical Simplicial (SymSimp) core with a depthwise separable structure, which allows to efficiently implement multi-channel convolutional layers by breaking 3D kernels into 2D kernels. The second is a 3×3 conventional MAC engine to implement the fully connected layers. Experimental results show an energy efficiency of 0.49pJ/OP, which is competitive when compared to similar technology ICs, and extrapolated to the MobileNetworkV2 ImageNet represents a factor of 2 improvement with respect to NVIDIA Jetson Nano.

Neuromorphic TinyML (vTinyML) aims at solving problems in machine perception and intelligence at the edge that necessitate low latency processing, using low resource processors that have neuromorphic event-based sensory interfaces and neuromorphic accelerators. In this paper, we report on a neuromorphic TinyML architecture (vMCU) which can be leveraged to be deployed to process data from event-based sensors on the edge. The core of the system is a RISC-V CPU from SiFive which is used for algorithm development. The CPU interfaces with a set of communication and computation peripherals which are comprised most notably of an event-based physical interface which has a 256Kib FIFO, a programmable 47-bit time-stamping unit and an embedded Compute in Memory (CiM) associative processor employing charge based processing and a pseudo-DRAM cell primitive. The vMCU SOC was fabricated in 65nm CMOS, has a die size of$7\text{mm}\times 4\text{mm}$, runs at 100MHz and has a maximum event throughput at its physical interface of 17Meps. Binary and integer operations on long bit vectors using the CiM accelerator capabilities take a few fJ per Op. vMCU capability consumes 30mW and is demonstrated in various tasks for embedded applications, including character recognition from a DAVIS240C event-based camera.

Neuromorphic processing architectures seek to emulate the functionality of the brain by realizing parallel, efficient, event-based processing which can be directly applied to solve many of the pressing problems within artificial intelligence and big data. However, implementation of these systems leads to slow response times, high power dissipation, or incoherent output. In this paper, an analog cellular neural network processing element is demonstrated to perform asynchronous spatiotemporal filtering operations in an area and power efficient manner. It utilizes a pair of analog memories to encode spike timings and perform event-based bandpass temporal processing. Information from the local clique of temporal filters is leveraged by a parallel, spatial processor which maps CNN arithmetic to the current-domain for compact computation. Preliminary circuit verification demonstrated the ability of the element to perform spatiotemporal filtering operations with latencies less than$1.8\mu\mathrm{s}$while only consuming 1.6pJ/spike.

Event-based vision cameras emulate the functionality of mamalian retina and promise to be a low-latency, energy efficient sensory front-end for machine perception. Despite the large-scale effort to deploy these sensors in a variety of scenarios, a proportionally small amount of effort has been devoted to the design and analysis of embedded architectures that process address events adjacent to the sensor. In this paper, a neuromorphic signal processing pipeline is reported which sparsifies the event stream thereby reducing energy consumption, increasing the signal-to-noise ratio, and improving downstream algorithm performance. It is integrated within a system-on-chip platform that will allow for the prototyping of different standards compliant, hardware modules within a embedded processing framework. We report two such modules which provides adaptive throughput management, spatiotemporal filtering, and programmable feature extraction.

Neuromorphic cameras that offer low latency and dynamic scene sensing are emerging as a viable technology for energy-aware embedded perceptual systems. In this paper we report on neuromorphic architecture and algorithm exploration for an event-based accelerator for neuromorphic cameras. The system includes a RISC-V CPU and associated peripherals that capture and process event-based visual data coming from a neuromorphic dynamic vision sensor. Mapped into a reconfigurable computing platform (FPGA), we demonstrate a set of event-based visual processing tasks including noise filtering, corner detection, and object tracking.

We discuss the architecture, implementation and testing of a neuromorphic Cellular Neural Network (CNN) processor for intelligent IoT devices. The processor is based on a simplicial piecewise linear CNN architecture that allows implementation of linear and nolinear CNNs. A linear array of 64 processing element (PE) with column-shared computation resources, tightly coupled to two data memory caches was synthesized and fabricated in a 55nm CMOS technology using custom layout libraries. The fabricated chip achieves an overall performance of 2.95 TOPS/W with dynamic energy dissipation efficiency of 86.4fJ per OP at V=500mV. The processor can implement different types of processing on 2D data arrays, such as gray-scale morphology, gradient flow, median filters, and approximate Gaussian filters, among others.