Fifth-generation (5G) wireless communications technologies and beyond are expected to provide new value as basic technologies supporting the future of industry and society. To meet challenging 5G requirements such as increased capacities, faster data speeds, and lower latencies, it is increasingly important to rapidly optimize an enormous number of parameters. This paper focuses on resource allocation in ultra-reliable low-latency communication (URLLC) when mini-slots are used to allow user equipments (UEs) to communicate simultaneously at lower latency. We also propose an efficient algorithm for ultra-low-delay allocation. URLLC resource allocation with mini-slot optimization is complicated, and it is difficult to find optimal solutions within the low delays that 5G requires, even when using a simulated bifurcation machine, which is known to solve the optimization problem at high speeds. Therefore, we propose a two-step algorithm. In the first step, we solve a relaxed optimization problem, for which the simulated bifurcation algorithm works well. In the second step, we find the desired resource allocation by solving another optimization problem using the solution found in the first step and prepared statistical information on that solution. The experimental results show that the proposed SBM algorithm can be applied to URLLC resource allocation and achieves better quality than a greedy algorithm. Furthermore, we showed that the resource allocation can be completed in less than 0.5 ms, as required to achieve the minimum transmission delay of the 5G specification.

We describe a cross-currency arbitrage machine using the simulated bifurcation (SB) algorithm for finding the most profitable exchange path from among many possible paths. SB is a recently proposed quantum-inspired algorithm for solving combinatorial optimization problems. The machine is an end-to-end arbitrage system implemented on a field-programmable gate array, in which a feed handler captures market packets issued at unscheduled intervals. An SB accelerator finds the optimal arbitrage path with a success probability of 90.96% by solving an optimal path-search problem in a directed graph, then a line handler issues an order packet within 30 microseconds after receiving the last market packet.

We present a cross-currency arbitrage system equipped with a custom accelerator for a simulated bifurcation algorithm to find optimal arbitrage opportunities, together with a market emulator that reproduces historical foreign exchange data feeds. We demonstrate that the system can capture short-lived (less than 1 millisecond lifetime) optimal arbitrage opportunities and respond to rapidly changing markets by issuing order packets within 30 microseconds after receiving market data feeds.

Since many combinatorial optimization problems can be mapped onto ground-state search problems of Ising models, special-purpose machines for Ising problems have attracted intense attention. Simulated bifurcation (SB) is a recently proposed algorithm to solve these Ising problems. One of the remarkable features of SB is the high-degree parallelism underlying in the algorithm, providing an opportunity to solve the Ising problems very fast by massively parallel processing. In this work, we implement the SB algorithm on FPGAs by designing massively parallel custom circuits. We then compare the FPGA-based SB machines with a state-of-the-art machine called a coherent Ising machine (CIM), a highly optimized implementation of simulated annealing (SA), and GPU-based SB machines. SB machines with spin size of 2,048/4,096 (2K/4K) on an Arria10 GX1150 FPGA have 8,192 processing elements for the matrix-vector multiplication (MM) modules (the most computationally intensive part) and achieve computation throughput of 1,873/2,027 GMAC/s for the MM modules, outperforming 2K/4K SB machines on an Nvidia Tesla V100 GPU (113/183 GMAC/s). The 2K FPGA-SB solves all-to-all connected 2000-node MAX-CUT problem 14X (/124X) faster than the CIM (/the highly-optimized SA), with much better energy efficiency (288X better than the CIM).

While plentiful on-chip memory is necessary for many designs to fully utilize an FPGA’s computational capacity, SRAM scaling is becoming more difficult because of increasing device variation. An alternative is to build FPGA block RAM (BRAM) from magnetic tunnel junctions (MTJ), as this emerging embedded memory has a small cell size, low energy usage, and good scalability. We conduct a detailed comparison study of SRAM and MTJ BRAMs that includes cell designs that are robust with device variation, transistor-level design and optimization of all the required BRAM-specific circuits, and variation-aware simulation at the 22nm node. At a 256Kb block size, MTJ-BRAM is 3.06× denser and 55% more energy efficient and its F max is 274MHz, which is adequate for most FPGA system clock domains. We also detail further enhancements that allow these 256 Kb MTJ BRAMs to operate at a higher speed of 353MHz for the streaming FIFOs, which are very common in FPGA designs and describe how the non-volatility of MTJ BRAM enables novel on-chip configuration and power-down modes. For a RAM architecture similar to the latest commercial FPGAs, MTJ-BRAMs could expand FPGA memory capacity by 2.95× with no die size increase.

Many important applications demand large amounts of on-chip memory both to fully utilize an FPGA's computational capacity and to minimize energy-consuming off-chip memory accesses, leading some recent commercial FPGAs to add higher-capacity on-chip block RAMs (BRAMs). While memory is becoming more important to FPGA designs, SRAM scaling is becoming more difficult because of increasing device variation. An alternative is to build FPGA BRAM from magnetic tunnel junction (MTJ) cells as this emerging embedded memory features a small cell size, low energy usage, and good scalability. In this work, we conduct a detailed comparison study of SRAM and MTJ BRAMs that includes cell designs that are robust with device variation, transistor-level design and optimization of all the required BRAM-specific circuits, and variation-aware simulation at the 22nm node. We find that as the capacity of a BRAM increases, the MTJ benefits of high-density and low-energy increase and its drawback of lower speed is mitigated. At a 256 Kb block size, MTJ-BRAM is 3.06× denser and 55% more energy efficient and its Fmaxis 274 MHz, which is adequate for most FPGA system clock domains. We detail how the non-volatility of an MTJ-BRAM saves energy, especially for narrow write operations which are common for the width-configurable BRAMs of FPGAs. For a RAM architecture similar to the latest commercial FPGAs, MTJ-based block RAMs reduce the FPGA fabric area by 28%, or alternatively could expand FPGA memory capacity by 2.95× with no die size increase.

Multi-context configuration memory stores multiple sets of configuration data and changes the entire configuration of FPGA quickly, enabling enhancement of hardware utilization with dynamic reconfiguration architectures. The memory area for one set of configuration data should be much smaller than the computational resource it controls. In this paper, we propose a pure-CMOS, nonvolatile, and small-footprint multi-context configuration memory. The multi-context memory includes multiple 2Tr nonvolatile memory elements, which are programmed by channel hot-electron injection, and allows context switching in a single clock cycle. A primitive dynamically reconfigurable device having a lookup table and minimum interconnect backed by 16-bit 8-context configuration memory was fabricated by a 0.18 um CMOS process and its functionality was demonstrated. The 2Tr nonvolatile memory element is more than 4 times denser than 6Tr SRAM, enabling achievement of greater logic density. The pure-CMOS and nonvolatile features would enhance the attractiveness of the technology in many applications.