Underwater wireless sensor networks (UWSNs) enable various oceanic applications which require effective packet transmission. In this case, sparse node distribution, imbalance in terms of overall energy consumption between the different sensor nodes, dynamic network topology, and inappropriate selection of relay nodes cause void holes. Addressing this problem, we present a relay-based void hole prevention and repair (ReVOHPR) protocol by multiple autonomous underwater vehicles (AUVs) for UWSN. ReVOHPR is a global solution that implements different phases of operations that act mutually in order to efficiently reduce and identify void holes and trap relay nodes to avoid it. ReVOHPR adopts the following operations as ocean depth (levels)-based equal cluster formation, dynamic sleep scheduling, virtual graph-based routing, and relay-assisted void hole repair. For energy-efficient cluster forming, entropy-based eligibility ranking (E2R) is presented, which elects stable cluster heads (CHs). Then, dynamic sleep scheduling is implemented by the dynamic kernel Kalman filter (DK2F) algorithm in which sleep and active modes are based on the node’s current status. Intercluster routing is performed by maximum matching nodes that are selected by dual criteria, and also the data are transmitted to AUV. Finally, void holes are detected and repaired by the bicriteria mayfly optimization (BiCMO) algorithm. The BiCMO focuses on reducing the number of holes and data packet loss and maximizes the quality of service (QoS) and energy efficiency of the network. This protocol is timely dealing with node failures in packet transmission via multihop routing. Simulation is implemented by the NS3 (AquaSim module) simulator that evaluates the performance in the network according to the following metrics: average energy consumption, delay, packet delivery rate, and throughput. The simulation results of the proposed REVOHPR protocol comparing to the previous protocols allowed to conclude that the REVOHPR has considerable advantages. Due to the development of a new protocol with a set of phases for data transmission, energy consumption minimization, and void hole avoidance and mitigation in UWSN, the number of active nodes rate increases with the improvement in overall QoS.

Probabilistic approaches to the detection of untargeted defects, such as n-detect and standard LBIST (logic built-in-self-test), generally suffer from the need to apply very long test sets to achieve good coverage. However, more targeted approaches that attempt to explicitly model new types of defects, such as cell-aware faults, so that they can be deterministically detected may also lead to unacceptably long test sets. Generally, when tests are applied to circuits that contain scan chains, test results are only captured once the entire pattern has been shifted in and the desired deterministic pattern has been applied. Intervening shift cycles serve only as overhead. This is done because capturing data in the circuit's scan flip-flops during scan shift would destroy the pattern being shifted in. However, if data is captured in shadow flops in a MISR instead, those shift cycles could be used to obtain additional fault coverage. In this paper, we investigate the ability of the intervening shift cycles to achieve high static cell-aware fault coverage using only the test patterns generated to detect stuck-at faults. We also investigate reducing the number of shadow flops required. Our results show that high cell-aware coverage is achievable even when only a stuck-at test set is applied — in some cases equal to the coverage obtained by a dedicated cell-aware test set.

3-D die-stacks hold great promise for increasing system performance, but difficulties in testing dies and assembling a 3-D stack are leading to yield issues and slowing the large scale manufacturing of these devices. In many cases, a single defective die will kill the entire stack. To help mitigate this issue, we explore the possibility of repairing a stack that contains a defective die by utilizing an field programmable gate array (FPGA) that has already been included in the stack for other purposes, such as performance enhancement. Specifically, we propose bypassing the defective portion of a nonprogrammable die by replacing the defective functionality with functionality on the FPGA. In this paper, we discuss what additional logic must be added to an Application-Specific Integrated Circuit (ASIC) die to allow such a bypass to occur. We then show through detailed simulation of a 2.5-D Xilinx FPGA how bypassing of logic can be achieved and throughput maintained even when the two different dies involved operate at different frequencies. Finally, we explore the performance of this technique in a superscalar, out-of-order processor, where different functional units are marked for replacement. Our simulation results show that not only can we salvage a device that would otherwise have to be discarded, but creating multiple copies of the defective partition in the FPGA can allow us to regain performance even when the latency of the units in the FPGA is longer than that of the original defective copy.