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Fumiharu Nakajima

dblp:161/5167 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2015
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › physical design › routing › detailed routing
grid routing
0.212015
Self-Aligned Double and Quadruple Patterning Aware Grid Routing Methods · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2015
Electronic design automation › physical design › lithography
multiple patterning lithography
0.212015
Self-Aligned Double and Quadruple Patterning Aware Grid Routing Methods · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2015
Electronic design automation
physical design
0.212015
Self-Aligned Double and Quadruple Patterning Aware Grid Routing Methods · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2015
Electronic design automation › physical design
routing
0.212015
Self-Aligned Double and Quadruple Patterning Aware Grid Routing Methods · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2015

Methods — techniques the papers use, named apart from their topics

graph coloring · 0.2dummy pattern flipping · 0.2
YearPublicationVenuePosition
2015 Self-Aligned Double and Quadruple Patterning Aware Grid Routing Methods
abstract
Although self-aligned double and quadruple patterning (SADP, SAQP) have promising processes for sub-20 nm node advanced technologies and beyond, not all layouts are compatible with them. In advanced technologies, feasible wafer image should be generated effectively by utilizing SADP and SAQP where a wafer image is determined by a selected mandrel pattern. However, predicting a mandrel pattern is not easy since it is different from the wafer image (or target pattern). In this paper, we propose new routing methods for spacer-is-dielectric (SID)-type SADP, SID-type SAQP, and spacer-is-metal (SIM)-type SADP to generate a feasible layout satisfying the connection requirements. Routing algorithms comprising simple connecting and cutting rules are performed on a new grid structure where two (SID-type SADP) or three colors (SID-type SAQP and SIM-type SADP) are assigned alternately to grid-nodes. Then a mandrel pattern is selected without complex coloring or decomposition methods. Also, we try to reduce hotspots (potentially defective regions) by the proposed dummy pattern flipping for SID-type SADP. In experiments, feasible layouts meeting the connection requirements are generated and the effectiveness of the proposed framework is confirmed.
Chikaaki Kodama, Hirotaka Ichikawa, Koichi Nakayama, Fumiharu Nakajima, Shigeki Nojima, Toshiya Kotani, Takeshi Ihara, Atsushi Takahashi 0001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.4