Steven M. Bowers

dblp:162/2650 · DBLP profile ↗
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4ranked-venue papers
0as first author
4since 2021 · last 2026
0000-0002-4243-8663ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 3 since 2021Computer networks · 1 · 1 since 2021
YearPublicationVenuePosition
2026 A 97.63 fJ/conv-step 3 GSa/s 2-Way Time-Interleaved (TI) 3-Bit Flash ADC for Analog In-Memory Computing (IMC) Deep Learning (DL) Accelerators in 28-nm CMOS
Jinhua Wang 0007, Adam H. Slater, Travis N. Blalock, Steven M. Bowers
ISCAS4
2025 A Sub-μW Digital Temperature Compensation Architecture for Arbitrary Voltage and Current Reference Generation
abstract
Traditionally, both reference circuits and the components they supply are designed independently to be as immune to temperature change as practical, but this requires power and area overhead to achieve. These overheads can compound in complex systems or consume excessive portions of a low power budget. In contrast, we propose a sub-μwatt digital temperature compensation architecture that generates voltage and current references with a user-defined temperature response rather than a fixed, near-ideal response. This flexible approach allows a single programmable design to be reused easily to produce different profiles over temperature, reducing design time. It also can reduce the temperature non-linearity in the components it supports by providing an input temperature profile that effectively cancels that non-linear response to allow components to operate at their target spec and eliminate excess power consumption. This approach allows designers to prioritize power consumption in their designs and use this compensation strategy to manage performance across temperature.
Natalie B. Ownby, Prerana Singaraju, Suprio Bhattacharya, Steven M. Bowers, Benton H. Calhoun
ISCAS4
2024 Integrated Two-way Radar Backscatter Communication and Sensing with Low-power IoT Tags
abstract
Integrated Sensing and Communication (ISAC) represents an innovative paradigm for enhancing spectrum and hardware utilization for both sensing and communication. A specific type of ISAC, radar backscatter communication, involves low-power nodes embedding data onto radar signal reflections rather than generating new signals. However, existing radar backscatter techniques only facilitate uplink communication from the tag to the radar, neglecting downlink communication. This paper introduces BiScatter, an integrated radar backscatter communication and sensing system that enables simultaneous uplink and downlink backscatter communication, radar sensing, and backscatter localization. This is achieved through the design of chirp-slope-shift-keying modulation on top of Frequency Modulated Continuous Wave (FMCW) radars, complemented by passive differential circuitry at the backscatter tags for low-power decoding. BiScatter also presents a packet structure compatible with off-the-shelf radars that offer accurate data processing and synchronization between radar and tag. We prototype this backscatter network in both 9GHz and 24GHz, demonstrating its capability to extend across different frequency bands. Our evaluations demonstrate that BiScatter supports two-way backscatter communication with BER lower than 10-3 up to 7m range and centimeter-level tag localization accuracy on top of off-the-shelf FMCW radars. The presented approach significantly augments the versatility and efficiency of ISAC for low-power devices.
Ryu Okubo, Luke Jacobs, Jinhua Wang 0007, Steven M. Bowers, Elahe Soltanaghai
SIGCOMM4
2021 Stacked Transconductance Boosting for Ultra-Low Power 2.4GHz RF Front-End Design
abstract
This paper presents a transconductance boosting method with a stacked current-reused inverter-based gain cell for ultra-low power RF applications. For the same bias current, the proposed method can boost the conventional inverter-based amplifier transconductance by twice, an overall quadruple boost compared to a single MOSFET in sub-threshold region. A 65nm CMOS based post-layout level implementation of the LNA including an on-chip matching network shows a 1.3 dB better noise figure as single inverter implementation for the same power of 45 μW. A cross-coupled stacked-gm VCO implementation achieves 44% higher voltage swing as that of the cross coupled single inverter at 74μA current, owing to the doubled gm value.
Anjana Dissanayake, Steven M. Bowers, Benton H. Calhoun
ISCAS2