Abir J. Mondal

dblp:162/3363 · DBLP profile ↗
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6ranked-venue papers
1as first author
4since 2021 · last 2025
0000-0001-8023-4103ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 1 first-author · 3 since 2021Applied, interdisciplinary, general and emerging computing · 1 · 1 since 2021
YearPublicationVenuePosition
2025 A Power Efficient One-Shot Rectangular Pulse Generator for Temperature Sensor
abstract
This work presents a power efficient one-shot rectangular pulse circuit made up of a delayed step pulse generator (MDSPG) followed by a variable rectangle pulse width generator (VRPWG) with auto termination. The MDSPG generates a delayed feedback signal and the VRPWG generates variable rectangular pulse with four different pulse width options. At 90-nm CMOS technology, the design occupies 0.0058 mm2and limits the power consumption between$5.78 \mu \mathrm{W}$to$5.81 \mu \mathrm{W}$at modes M0 and M3, respectively. Additionally, the proposed architecture ensures a large span of rectangular pulse width ranging from$155.66 \mu \mathrm{s}$to$1247.96 \mu \mathrm{s}$at M0 and M3, respectively. The proposed design is a suitable choice for a multi-mode resolution and multi conversion time-domain temperature sensor. A subthreshold time-to-digital converter is accommodated to realize the sensor in a 90-nm CMOS and the area is limited to 0.011 mm2. Lastly, the resolution varies between 0.29° C and 0.036° C at modes M0 and M3, respectively.
Kuntal Chakraborty, Subhajit Das 0001, Abir Chattopadhyay, Abir J. Mondal
TENCON4
2024 On-chip oscillator based temperature-to-digital converter exploiting channel length modulation coefficient λ
Kuntal Chakraborty, Abir J. Mondal
Integr.2
2022 A low power and PVT variation tolerant mux-latch for serializer interface and on-chip serial link
Mithilesh Kumar 0008, Alak Majumder, Abir J. Mondal, Arijit Raychowdhury, Bidyut K. Bhattacharyya
Integr.3
2021 A PVT aware differential delay circuit and its performance variation due to power supply noise
Anirban Tarafdar, Abir J. Mondal, Uttam Kumar Bera, Bidyut K. Bhattacharyya
Integr.2
2017 Threshold adjustment of receiver chip to achieve a data rate >66 Gbit/sec in point to point interconnect
Alak Majumder, Abir J. Mondal, Bidyut K. Bhattacharyya
Integr.2
2017 A mathematical formulation to design and implementation of a low voltage swing transceiver circuit
Abir J. Mondal, Alak Majumder, Bidyut K. Bhattacharyya
Integr.1