Although wake-up power-supply noise (PSN) leaves a more profound mark on IC performance than run-time PSN, it has received little attention in contemporary studies. This article addresses this gap by presenting a comprehensive mathematical model of wake-up PSN and introducing a novel strategy to temporally spread its impact via frequency modulation during the IC's sleep-to-active transition. Bringing this concept to reality, a framework of Sweeping Variable-Frequency Clock (SVFC) synthesis was realized in SCL 180 nm CMOS. Rigorous postlayout simulations on Cadence Virtuoso at a supply of 1.8 Volt reveal its finesse-achieving sub-10ps jitter and nearly 50% consistent pulse width across all frequencies and all process corners. Finally, benchmark analyses under DIP-40 package model substantiate the effectiveness of the approach with an average 63.6% improvement in wake-up PSN and 65.7% current and power savings across circuits under test, demonstrating a pathway to mitigate wake-up PSN and enhance IC reliability.

This paper presents HexLock, a compact and energy-efficient ASIC-based digital locking system that employs a4-bit hexadecimal key architecturefor secure hardware-level access control in embedded and consumer electronic applications. Unlike traditional microcontroller-based locks, it eliminates firmware dependencies and operates using fully synchronous, power gated digital logic, significantly reducing power and area overhead. The system accepts parallel 16-bit binary key input or 4-bit sequential hexadecimal key inputs, and verifies them through a pipelined XOR-OR logic against a configurable stored code, enforcing tamper resistance via an on-chip false attempt counter and early mismatch termination logic. Designed and verified on SCL 180nm CMOS node, HexLock records a core layout area of 0.35mm2and post-layout delay of 4.5 ns along with dormant and active power consumption of 4.76 μW and 0.15 mW respectively under typical operating conditions. Functional validation across full PVT corners (-20°C to 120°C) confirms reliable operation up to 85 MHz. As summarized in Table IV, HexLock achieves substantially lower active power and a smaller silicon footprint compared to standard MCU and FPGA based locking alternatives, thereby eliminating firmware dependencies through hardware-only authentication. These properties make HexLock a practical candidate for integration in smart locks, IoT platforms, and safety-critical consumer systems.

Power supply noise (PSN) in central processing unit (CPU) cores or any integrated circuit (IC) chips is a problem of power line voltage degradation impelled due to the parasitic components (viz., resistance, capacitance, and inductance) across the packaging. This lowers the operating frequency of the silicon chip during high volume manufacturing and thereby, affects the overall performance. After numerous attempts to minimize the parasitic impacts of power delivery networks (PDNs) in IC packages, researchers also started to look for circuital configurations that can curb down the coefficients of PSN (i.e., the instantaneous current$i(t)$and the current ramp$[({di(t)})/{dt}]$during OFF to ON switching of packaged CPU/IC). Though variable frequency clock (VFC) has emerged as a potential solution, its design is found to be complex and power hungry. Hence, a novel and simple configuration of VFC embedded with leakage control transistor-based clock gating (LCT-CG) is tendered in this article, where the pertaining circuits and integrated system have been designed using UMC 65 nm CMOS with a supply of 1.1 V. The performance of the design is tested on master-slave flip-flop (MSFF) and a few prominent benchmark circuits (viz., ISCAS’89 s27, s820, s832, s1196, s9234 and ITC’99 b02 and an IEEE 754 complaint single precision FPU) considering the PDN of existing CPU OLGA package. The system-level validation of our proposed IC on A-Z80 CPU chip offers the average power and PSN to be mitigated by 30.06% and 42.63% against the conventional clocking.