This paper describes an expandable digital delay line to achieve both a wide delay range and fine delay resolution. The proposed delay line has coarse and fine delay lines with almost identical unit delay cells. The coarse delay line has a classical configuration of cascaded connection for easy expansion of the delay range. The fine delay line applies phase interpolation to the signals before and after the unit delay cell for fine delay resolution. This architecture allows easy expansion of the delay range while keeping the fine resolution. The delay line also has duty cycle corrector for the clock signal using the simple structure of additional PMOS and NMOS onto the phase-mixing node. Measurement results of the test-chip show the basic concept of the proposed delay line was effective. This delay line has a well-balanced performance and achieves the finest resolution (almost half) of any published delay lines with a delay range of 1 ns or greater.

This paper describes a Fractional-N Phase Locked Loop (PLL) for multi-phase (=M) clock generation by reducing capacitor area. The M-phase clocks from the Voltage Controlled Ring Oscillator (VCO) have a frequency between N and N+1 times of a reference clock by second-order Delta Sigma Modulator (DSM). The reference clock is divided into M-phase clocks by Delay Locked Loop (DLL). The DSM assigns N or N+1 to a programmable divider (DIV), and the M DIV and DSM are prepared to feed M-phase divided VCO clocks. The divided VCO clocks and the reference clocks are compared respectively during one cycle of the input clock. This PLL system is equivalent to multiplying the input clock frequency by M, and the loop bandwidth of the PLL can be wider (×M) by reducing the capacitance value to one-Mth (÷M) in a loop filter (LF). To achieve the system, i) the divided VCO clocks should be generated by adding appropriate delay, and ii) the threshold value of each DSM has to be set properly. Measurement results of a test chip show equivalent frequency fluctuation and phase jitter of VCO clocks between conventional PLL with capacitance value C and the proposed PLL with capacitance value C÷M.

In this paper, simple and compact Negative Bias Temperature Instability (NBTI) model is proposed. The model is based on the reaction-diffusion (tn) and hole-trapping (log(t)) theories. A single shot of DC stress and recovery data is utilized to express duty cycle dependence of NBTI degradation and recovery. Parameter fitting is proceeded by considering that the amount of recovery cannot be larger than stress degradation. The proposed model successfully replicates stress and recovery with various duty cycles.