This paper presents a SystemVerilog-based modeling and simulation methodology for a 4-level pulse-amplitude-modulation (PAM-4) transceiver. The framework is developed to address verification challenges in complex analog-to-digital converter (ADC)-based mixed-signal systems, where conventional circuit-level simulations suffer from prohibitively long execution time. Two key modeling techniques to significantly improve simulation efficiency are introduced in this work. For the time-interleaved ADC (TI-ADC), a counter-based equivalent circuit model is employed to capture dominant rank-1 mismatch errors while substantially reducing modeling complexity. In addition, for digital clock and data recovery (CDR), a statistical bit-error-rate (BER) evaluation approach based on XMODEL primitives is adopted as an alternative to conventional time-domain analog-mixed-signal (AMS) simulations. This modeling framework enables accurate verification of critical transceiver performance metrics, such as jitter tolerance (JTOL), within a 30-minute simulation window. Compared to conventional timedomain simulations, which require more than 12 hours to perform, the proposed approach achieves approximately a 24× improvement in simulation speed.

Frequency multipliers are increasingly utilized for signal up-conversion in modern wireless communication systems, particularly in millimeter-wave (mmWave) and sub-terahertz (sub-THz) bands, owning to their simplicity and ease of integration. However, their inherent nonlinearity causes distortions, fundamentally altering the temporal and spectral characteristics of transmitted signals. This distortion transforms well-defined baseband pulses (e.g., sinc, raised cosine) into complex, hardware-dependent waveforms, where the matched-filter depends both on the multiplication order and the specific hardware implementation. Notably, the spectral occupancy of the transmitted signal expands after frequency multiplication. Without accurate knowledge of the multiplier-induced distortions at the receiver, applying a mismatched filter can cause severe inter-symbol interference and loss of critical frequency components, signal-to-noise ratio degradation thereby degrading detection performance. In this paper, we propose a blind, adaptive matched-filter estimation approach leveraging a Long Short-Term Memory (LSTM) neural network. Our method directly estimates the matched filter from sampled segments of the noisy modulated received signal without requiring pilot symbols. The proposed model adapts to dynamic pulse shapes and amplitudes by implicitly learning the spectral transformations introduced by hardware-induced nonlinearities. Simulation results demonstrate high accuracy of the matched filter estimation, with a mean-square error precision of four decimal places.

Even though Terahertz (THz) band is promising for Drone-to-Drone (D2D) communication, there exists significant challenges, primarily high path loss and the sensitivity of directional links to mobility-induced beam misalignment. In this paper, we propose a novel adaptive beamwidth control system for THz D2D communication by activating rows of the designed 8×8 microstrip patch antenna array operating at 272.5 GHz. The proposed row-selective activation mechanism provides dynamic adjustment of the elevation beamwidth by activating different combinations of antenna rows (from 1×8 to 8×8 configurations). The proposed mechanism offers a flexible trade-off in its beam characteristics, utilizes narrow, high-gain beams to maximize performance in stable links, and dynamically switches to wider, more robust beams to ensure connectivity during drone maneuvers. The performance of the reconfigurable array is evaluated through real drone mobility traces. Simulation results reveal that during periods of misalignment, the adaptive beamwidth strategy maintains link capacity that is up to three orders of magnitude higher than fixed-beam configurations, promising a practical solution for resource-constrained THz D2D communication.

A 300GHz CMOS-only wireless transceiver that achieves a maximum data rate of 34Gb/s while consuming a total power of 0.41W from a 1V supply is introduced. A subharmonic mixer with low conversion loss is proposed to compensate the absence of the RF amplifiers in TX and RX as a mixer-last-mixer-first topology is adopted. The TRX covers 19 IEEE802.15.3d channels (13-23, 39-43, 52-53, 59).

This paper presents a relative slope-boosting technique for a capacitive sensor circuit based on a relaxation oscillator. Our technique improves jitter, i.e. resolution, by changing both the voltage slope on the sensing and the reference sides with respect to the sensor capacitance. The sensor prototype circuit is implemented in a 180-nm standard CMOS process and achieves resolution of 710 aF while consuming 12.7 pJ energy every cycle of 13.78 kHz output frequency. The measured power consumption from a 1.2 V DC supply is 430 nW.

This work presents a current-starved cross-coupled chaotic oscillator achieving multiple decades of oscillation frequency spanning 2 kHz to 15 MHz. The main circuit characteristics are low-power consumption (<100 nW to 25 μW, at 1 V supply voltage), and controllability of the oscillation frequency, enabling future applications such as in distributed environmental sensing. The IC was implemented in 180 nm standard CMOS process, yielding a core area of 0.028 mm2.

This work presents five different 8-bit fixed point low power hardware implementations of cow behavior classifying axis-parallel decision trees (DT) for a range of five feature sets (FS). Each DT is trained and tested with 3-axis accelerometer data labeled beforehand containing four main behaviors, resting, eating, rumination and moving. Investigation shows a 10% F1- score decrement from software (77.4%) to 8-bit fixed point hardware (67.4%) for the conventional feature set, i.e. average mean and variation of the 3D accelerometer vector magnitude (FS4) due to quantization. The horizontal-longitudinal angle of acceleration of the cow (arctan2(y, x)) is proposed as a new FS together with the vertical z-axis (FS1&FS2). The results of an experimental setup, which simulates a stratified 20% split of the entire dataset from PC to FPGA, shows an average accuracy of 86.81% respectively for FS2. This FS's hardware implementation programmed on a Lattice ICE40UP5K FPGA has a power consumption of 216 μW with a latency of 2.58 s at the frequency of 2.9 kHz resulting in an energy of 557 J per classification, which is competitive with state of the art.

In this paper, a way to realize 1Tbps in wireless will be discussed based on Shannon and Friis equations. Several millimeter-wave CMOS transceivers will be also introduced to show possible ways to realize more than 100Gb/s data rate by using the present circuit and device technology. The importance of active and passive device characterization is provided and examples are given with relevant references.

A W-band ultra-high data-rate (56Gb/s) wideband (68-102GHz) 65nm bulk CMOS wireless transceiver is presented. Frequency interleaving by two up-converted IF data signals using 68 and 102GHz LO to W-band is applied to achieve wideband and a world-record 56Gb/s wireless communications on CMOS. 16QAM modulation is used for 6.5GHz (26Gb/s) low-band and 7.5GHz (30Gb/s) high-band data. Transmitter/receiver (TX/RX) consumes 260/300mW from 1V DC supply.