This paper presents a 1 GHz low power Direct Digital Synthesizer (DDS) with sub-Hertz frequency resolution operating at 9.4 K. The proposed circuit is used as a signal generator for microwave (MW) driven qubit entanglement operations in trapped-ion quantum computers for improved gate fidelity. This is realized by utilizing the generated waveform as the carrier for the qubit’s driving signal. This signal is further frequency multiplied and envelope modulated to get the final qubit driving signal. The proposed mixed-signal-circuit operates at a 2.5 V/1.5 V analog and 1.5 V digital supply, 1 GHz input clock and consumes a total power of 27.64 mW. The frequency normalized-total power consumption, is only 27.64 µW/MHz. The DDS gives a worst case narrow band SFDR of 32.72 dB across the octave of frequencies to be synthesized. The design is manufactured in a 0.13 µm SiGe BiCMOS technology and has a core area of 0.69 mm2.

This paper presents an overview of the latest research results on integrated, cryogenic-compatible electronics for ion shuttling operation in Trapped-Ion Quantum Computers (TIQCs). Integrated circuit (IC) realization is essential to enable system scaling towards a larger number of qubits. Firstly, we review the specific challenges related to the shuttling operation and ion confinement. Consequently, implications on circuit design of an integrated shuttling controller system on chip (SoC) are discussed. Particularly, among other circuit design parameters, we analyze in detail the requirements on power and area consumption, noise performance, and cryogenic-compatibility. Secondly, we provide an overview on reported discrete solutions, eventually highlighting the need for a dedicated integrated shuttling controller SoC. Hence, state of the art integrated shuttling controller approaches are presented and reviewed. Finally, we conclude the paper with an outlook on promising integrated circuit concepts for shuttling controllers.

The realization of autonomous, wearable, and implantable system-on-chip (SoC) for health monitoring applications poses several challenges, such as achieving ultralow size, cost, and power consumption, yet offering sufficient flexibility to reprogram and adapt the autonomously operating SoC during the course of treatment. Commonly, programmability is not considered for ultralow-power (ULP) biomedical SoCs, since a dedicated finite state machine (FSM) fixes the operation sequence, and instruction memory presents significant contributions to silicon area and power consumption. Based on a previously published tiny, programmable microarchitecture, this work proposes the strongly enhancedNanoController v2, for potential use in ultralow-power biomedical SoCs, and integrates it as a prototype chip in a 22-nm FDSOI-CMOS technology. By implementing a novel microcoded control unit and an automated design space exploration framework, which are made available open-source, the instruction set can be freely redefined to exploit application-specific properties. The benefits are increased code compaction, performance gain, and, consequently, decreased power consumption. In an extensive measurement campaign, a glucose sensor control application achieves 13.1% higher performance and 15.6% less code size in the best case, resulting in an extremely low power consumption of 660 nW (9% less than the reference),only by a different instruction setwithout hardware changes. Compared with other state-of-the-art small programmable microcontrollers, between 38% and 82% smaller code size and between 33% and 77% smaller silicon area and averaged power consumption could be shown. Based on the prototype results, a fully integrated glucose sensor chip will be evaluated in currently ongoing work.

This work presents an ultra-low-power, single-ended successive approximation register (SAR) analog-to-digital converter (ADC) designed explicitly to digitize sensor data. Due to the single-ended nature of the sensor’s output data, very efficient designs for differential SAR ADCs cannot be utilized. Hence, a monotonic capacitor switching procedure for single-ended inputs has been developed and is introduced in this paper. Re-charging of capacitances during the SAR algorithm is no longer required, resulting in significant energy savings compared to conventional approaches.The SAR ADC is implemented in a 22nm CMOS FDSOI technology. It achieves a measured signal-to-noise and distortion ratio (SNDR) of 49.1dB and a spurious-free-dynamic-range (SFDR) of 61dB. It draws a simulated 1.2μW yielding a Walden figure of merit (FoMW) of 50.2fJ/conversion step at a sampling rate of 100kS/s. The circuit occupies an area excluding pads of only 275 x 220μm2.

This paper presents a low-noise low-dropout regulator (LNLDO) implemented in a 28 nm technology. The LNLDO features a two-stage architecture, using a low-pass filter with a very low cut-off frequency to separate the regulation loop and the noisy devices such as resistive divider and bandgap reference. Supplied by a 1.5 V-1.8 V input voltage, the LNLDO is able to provide a stable output voltage ranging from 0.73 V to 1.71 V, with a current supply ability from 0 to 35 mA. An on-chip capacitance enhancer is used to stabilize the regulation loop without an additional external capacitor. The RMS noise from 10 Hz to 100 kHz of the LNLDO is below 20μV.

Image-based patient-specific modelling of hemodynamics are gaining increased popularity as a diagnosis and outcome prediction solution for a variety of cardiovascular diseases. While their potential to improve diagnostic capabilities and thereby clinical outcome is widely recognized, these methods require considerable computational resources since they are mostly based on conventional numerical methods such as computational fluid dynamics (CFD). As an alternative to the numerical methods, we propose a machine learning (ML) based approach to calculate patient-specific hemodynamic parameters. Compared to CFD based methods, our approach holds the benefit of being able to calculate a patient-specific hemodynamic outcome instantly with little need for computational power. In this proof-of-concept study, we present a deep artificial neural network (ANN) capable of computing hemodynamics for patients with aortic coarctation in a centerline aggregated (i.e., locally averaged) form. Considering the complex relation between vessels shape and hemodynamics on the one hand and the limited availability of suitable clinical data on the other, a sufficient accuracy of the ANN may however not be achieved with available data only. Another key aspect of this study is therefore the successful augmentation of available clinical data. Using a statistical shape model, additional training data was generated which substantially increased the ANN's accuracy, showcasing the ability of ML based methods to perform in-silico modelling tasks previously requiring resource intensive CFD simulations.

Industrial food production is one of the biggest businesses that supplies most of the food consumed by the world. Despite being one of the largest industries, the lack of appropriate control and quality due to inefficient food management results in a lot of waste and cost ineffectiveness. With the emergence of Internet of Things (IoT) and Industry 4.0, the food industry can be benefited by adapting to these concepts and enhance the desirable quality of the products. In this paper, an advanced quality check method has been proposed by identifying influencing process parameters and proposes a retrofitting architecture for existing machines by implementing a hardware device capable of collecting vast amount of process data and integrating them with a cloud platform for further analysis.